A Reconfigurable Fabric For Accelerating Large-Scale Datacenter Services

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Even if Dennard scaling came to an end fifteen years ago, Moore' s law kept fueling an exponential growth in compute performance through increased parallelization. However, the performance of memory and, in particular, Dynamic Random Access Memory (DRAM), ...

Joint Photographic Experts Group (JPEG) XS is a new International Standard from the JPEG Committee (formally known as ISO/International Electrotechnical Commission (IEC) JTC1/SC29/WG1). It defines an interoperable, visually lossless low-latency lightweight ...

Novel applications have triggered significant changes at the system level of FPGA architecture design, such as the introduction of embedded VLIW processor arrays and hardened NoCs. However, the routing architecture of the soft logic fabric has largely rema ...

True random number generators (TRNGs) allow the generation of true random bit sequences, guaranteeing the unpredictability and perfect balancing of the generated values. TRNGs can be realised from the sampling of quantum phenomena, for instance, the detect ...

Despite FPGAs rapidly evolving to support the requirements of the most demanding emerging applications, their high static power consumption, concentrated within the routing resources, still presents a major hurdle for low-power applications. Augmenting the ...

Low-inertia grids are characterized by high shares of harmonic and inter-harmonic distortion, produced by the inverters that interface non-conventional generation assets to the electrical grid. These interfering tones largely compromise synchrophasor estim ...

Binary logic gates are building blocks of computing machines, in particular, electronic computers. One variant is the programable logic gate, also known as the reconfigurable logic gate, in which the logical function implemented can be modified. In this pa ...

Binary logic operations are the building blocks of computing machines. In this paper, we present a new programmable binary logic gate based on programmable multistable mechanisms (PMM), which are multistable structures whose stability behavior depends on m ...

The time-reversal invariance is readily described and universally embodied in most laws of nature, either in a strict or in a soft sense. Based on this underlying physical principle, time-reversal theory has been theoretically and experimentally studied in ...

This work presents a technique to produce random bits by exploiting single-photon time of arrival. Two quantum random number generator (QRNG) devices based on the field programmable gate array (FPGA) technology are presented: Randy, which uses one discrete ...

The growing importance of applications based on machine learning is driving the need to develop dedicated, energy-efficient electronic hardware. Compared with von Neumann architectures, which have separate processing and storage units, brain-inspired in-me ...

Recent works have demonstrated the possibility of extracting secrets from a cryptographic core running on an FPGA by means of remote power analysis attacks. To mount these attacks, an adversary implements a voltage fluctuation sensor in the FPGA logic, rec ...

A Reconfigurable Fabric For Accelerating Large-Scale Datacenter Services

Chat with Graph Search

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

JPEG XS-A New Standard for Visually Lossless Low-Latency Lightweight Image Coding

NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs

Certification of the efficient random number generation technique based on single-photon detector arrays and time-to-digital converters

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

Design and experimental validation of an FPGA-based PMU simultaneously compliant with P and M performance classes

Reconfigurable Logic Gates Based on Programable Multistable Mechanisms

Programmable Logic Gates Based On Tunable Multistable Mechanisms

Electromagnetic Time Reversal: Theory, Application to Fault Location in Power Networks and Experimental Validation

Efficient random number generation techniques for CMOS single-photon avalanche diode array exploiting fast time tagging units

Logic-in-memory based on an atomically thin semiconductor

Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks?