Design and experimental validation of an FPGA-based PMU simultaneously compliant with P and M performance classes

Low-inertia grids are characterized by high shares of harmonic and inter-harmonic distortion, produced by the inverters that interface non-conventional generation assets to the electrical grid. These interfering tones largely compromise synchrophasor estimation and may jeopardize protection and control strategies based on Phasor Measurement Units (PMU). Indeed, the IEEE Std. C37.118 does not require resiliency against inter-harmonic tones for protection PMUs. In view of increasing synchrophasor technology reliability, the paper presents the design and the experimental validation of a PMU that is simultaneously compliant with both protection (P) and measurement (M) class of PMU performance defined in the IEEE Std. C37.118. The synchrophasor estimator is based on the interpolated DFT and iteratively estimates and compensates the effects of the spectral interference produced by a generic interfering tone and the negative image of the fundamental tone. The proposed hardware architecture is based on a Field Programmable Gate Array (FPGA).