Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

The engineering of tin halide perovskites has led to the development of p-type transistors with field-effect mobilities of over 70 cm2 V-1 s-1. However, due to their background hole doping, these perovskites are not suitable for n-type transistors. Ambipol ...

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

The versatility of half-bridge configuration of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power module contributes to its widespread adoption, highlighting the popularity and significance of its corresponding dual gat ...

In the past decades, a significant increase of the transistor density on a chip has led to exponential growth in computational power driven by Moore's law. To overcome the bottleneck of traditional von-Neumann architecture in computational efficiency, effo ...

This paper highlights some of the challenges faced in the modeling of MOSFET devices operating at cryogenic temperature (CT). It will review the most important phenomena, including the saturation of the subthreshold swing (S S) below a critical temperature ...

5G New Radio (NR) has stringent demands on both performance and complexity for the design of low-density parity-check (LDPC) decoding algorithms and corresponding VLSI implementations. Furthermore, decoders must fully support the wide range of all 5G NR bl ...

We present a single-photon avalanche diode (SPAD) developed in 55 nm bipolar-CMOS-DMOS (BCD) technology, which achieves high photon detection probability (PDP) while its breakdown voltage is lower than 20 V. To enhance the PDP performance, the SPAD junctio ...

Applications demanding imaging at low-light conditions at near-infrared (NIR) and short-wave infrared (SWIR) wavelengths, such as quantum information science, biophotonics, space imaging, and light detection and ranging (LiDAR), have accelerated the develo ...

The digital revolution has significantly transformed our world over the past decades, driven by the scaling of transistor dimensions and the exponential increase in computation power. However, as the CMOS scaling era approaches its end, the semiconductor i ...

Quantum random number generators (QRNGs) are a burgeoning technology used for a variety of applications, including modern security and encryption systems. Typical methods exploit an entropy source combined with an extraction or bit generation circuit in or ...

Organic electrochemical transistors (OECTs) have gained enormous attention due to their potential for bioelectronics and neuromorphic computing. However, their implementation into real-world applications is still impeded by a lack of understanding of the c ...

In this article, we consider decentralized optimization problems where agents have individual cost functions to minimize subject to subspace constraints that require the minimizers across the network to lie in low-dimensional subspaces. This constrained fo ...

Defects in solids are unavoidable and can create complex electronic states that can significantly influence the electrical and optical properties of semiconductors. With the rapid progress in the integration of 2D semiconductors in practical devices, it is ...

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

In 1948, Claude Shannon laid the foundations of information theory, which grew out of a study to find the ultimate limits of source compression, and of reliable communication. Since then, information theory has proved itself not only as a quest to find the ...

In this work, we propose an analytical model for the intrinsic transcapacitances in ultra-thin gate-all-around junctionless nanowire field effect transistors in the presence of confined energy states of electrons. The validity of the developed model is con ...

Vision systems built around conventional image sensors have to read, encode and transmit large quantities of pixel information, a majority of which is redundant. As a result, new computational imaging sensor architectures were developed to preprocess the r ...

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

There is a never-ending push for electronic systems to provide faster operation speeds, higher energy efficiencies, and higher power capabilities at smaller scales. These requirements are apparent in different areas of electronics, from radiofrequency (RF) ...

Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit

Chat with Graph Search

Strain relaxation and multidentate anchoring in n-type perovskite transistors and logic circuits

Highly Parallel RTL Simulation

EdgeAI-Aware Design of In-Memory Computing Architectures

Active Voltage Balancing with Seamless Integration into Dual Gate Driver for Series Connection of SiC MOSFETs

Towards Scalable Electronics: Synthetic 2D Materials for Large-Area 2D Circuit Integration

Modeling of the MOSFET for the Design of Cryo-CMOS Circuits

A Generalized Adjusted Min-Sum Decoder for 5G LDPC Codes: Algorithm and Implementation

SPAD Developed in 55 nm Bipolar-CMOS-DMOS Technology Achieving Near 90% Peak PDP

Silicon CMOS and InGaAs(P)/InP SPADs for NIR/SWIR detection

Energy-Efficient Electronic Functions Based on the Co-integration of 2D and Ferroelectric Materials

A 3.3-Gb/s SPAD-Based Quantum Random Number Generator

Unraveling the Electrochemical Electrode Coupling in Integrated Organic Electrochemical Transistors

Quantization for Decentralized Learning Under Subspace Constraints

Electrical spectroscopy of defect states and their hybridization in monolayer MoS2

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Time vs. Truth: Age-Distortion Tradeoffs and Strategies for Distributed Inference

Transcapacitances Modeling in ultra-thin gate-all-around junctionless nanowire FETs, including 2D quantum confinement

Computational Imaging SPAD Cameras

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

New ultrahigh-speed device concepts: from THz nanoplasma devices to glass-like electronics for neuromorphic computation