Publications related to A DAC Mismatch Calibration Technique for Multibit Sigma Delta Modulators

Related publications (27)

Cascaded all-optical quantization employing step-size MMI and shape-optimized power splitter

As a key unit of future high-throughput communications, optical analog to digital converter (OADC) with all-optical quantizer element that simultaneously possesses high resolution, large bandwidth and compact size is highly promising. A pending issue of co ...

ELSEVIER SCI LTD2023

An Error-Based Approximation Sensing Circuit for Event-Triggered Low-Power Wearable Sensors

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Tomas Teijeiro Campo, Flavio Ponzina, Silvio Zanoli

Event-based sensors have the potential to optimize energy consumption at every stage in the signal processing pipeline, including data acquisition, transmission, processing, and storage. However, almost all state-of-the-art systems are still built upon th ...

2023

An All-Digital 1.25 Mbps 5-Subcarrier OFDM Backscatter Uplink with Delta-Sigma Modulation for Improved Spurious-Free Dynamic Range

James Daniel Rosenthal

This paper describes an all-digital backscatter modulation approach leveraging delta-sigma modulation (DSM) to improve the in-channel spectral characteristics of orthogonal frequency division multiplexed (OFDM) backscatter communication. We demonstrate thr ...

IEEE2022

Spike-Based Sensing and Communication for Highly Energy-Efficient Sensor Edge Nodes

Mihai Adrian Ionescu, Teodor Rosca

Highly energy-efficient wireless sensor nodes are a prerequisite for a sustainable operation of the Internet of things. Therefore, classical approaches for system design based on digital signal processing are not a viable solution, but system design has to ...

IEEE2022

A Delta Sigma-Modulated Sample and Average Common-Mode Feedback Technique for Capacitively Coupled Amplifiers in a 192-nW Acoustic Analog Front-End

Kyojin Choo

This work presents an acoustic analog front-end based on a delta sigma-modulated sample and average common-mode feedback technique. The proposed feedback offers a process and temperature stable high pass (HP) frequency corner, unity dc feedback gain, and a ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

High-Speed ADC Design and Optimization for Wireline Links

Ayça Akkaya

The ever-growing global internet traffic has increased demand for higher speed data transmission. As the bandwidth requirements of wireline links increase, extensive digital equalization techniques are required to compensate for the high-frequency channel ...

EPFL2021

A 32 Gb/s PAM-16 TX and ADC-Based RX AFE with 2-tap embedded analog FFE in 28 nm FDSOI

Yusuf Leblebici, Firat Çelik, Ayça Akkaya

This paper presents a 32 Gb/s 16-level pulse amplitude modulation (PAM-16) source-series-terminated transmitter (TX) and a receiver (RX) analog front-end (AFE) in 28 nm FDSOI. The 8-way time-interleaved successive-approximation register (SAR) analog-to-dig ...

2021

Energy-Efficient Design Techniques for High-Speed Wireline Serial Links

Firat Çelik

The exponential growth in computing power and multimedia services has caused a tremendous increase in data traffic in recent years. This increase in data traffic brings a strong demand for data bandwidth of electrical input/output (I/O) links and pushes th ...

EPFL2021

Asynchronous sar adc with unit length capacitors and constant common mode monotonic switching

Volkan Cevher, Arda Uran

A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) comprising a Track-and-Hold (T/H) switch configured for a sampling of an input voltage in the form of charge onto a capacitor; a Capacitive Digital-to- Analog Converter (CD AC) opera ...

2021

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Yusuf Leblebici, Andreas Peter Burg, Alessandro Cevrero, Thomas Toifl, Lukas Kull, Ilter Ozkaya, Gain Kim, Cosimo Aprile

This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates a fully digital equalization data-path, with a synthesized and automatically placed a ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Coded LoRa Frame Error Rate Analysis

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Orion Afisiadis

In this work, we study the coded frame error rate (FER) of LoRa under additive white Gaussian noise (AWGN) and under carrier frequency offset (CFO). To this end, we use existing approximations for the bit error rate (BER) of the LoRa modulation under AWGN ...

IEEE2020

High Speed SAR ADC Architectures in 28nm FDSOI CMOS

Mustafa Kilic

The demand on high speed Analog to Digital Converters (ADCs) has increased considerably the last years. From communications circuit to high speed oscilloscopes, Giga Samples per second (GS/s) ADCs are requested. With the scaling of the CMOS technology, des ...

EPFL2019

Adaptive simulation-based framework for error characterization of inexact circuits

Vincent Frédéric Camus

To design faster and more energy-efficient systems, numerous inexact arithmetic operators have been proposed, generally obtained by modifying the logic structure of conventional circuits. However, as the quality of service of an application has to be ensur ...

PERGAMON-ELSEVIER SCIENCE LTD2019

Gaussian channel transmission of images and audio files using cryptcoding

Random codes based on quasigroups (RCBQ) are cryptcodes, i.e. they are error-correcting codes, which provide information security. Cut-Decoding and 4-Sets-Cut-Decoding algorithms for these codes are defined elsewhere. Also, the performance of these codes f ...

2019

An Eight lanes 7Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels

Yusuf Leblebici, Volkan Cevher, Alessandro Cevrero, Thomas Toifl, Lukas Kull, Cosimo Aprile

This paper presents a versatile crosstalk cancellation scheme for single-ended multi-lane backplane links. System-level investigations show that a scheme, which combines analog filters and decision-feedback crosstalk compensation on the receiver (RX) side ...

2018

High-Speed Wireline Link Design

Hazar Yüksel

High-speed serial links are a crucial application of semiconductor technology and have been the enabler of the scaling of computing systems. The increasing data-rate requirements of these links have only been partially satisfied by advancements in process ...

EPFL2017

A DAC Assisted Speed Enhancement Technique for High Resolution SAR ADC

Yusuf Leblebici, Mustafa Kilic

In this paper, a technique aiming at enhancing the conversion speed of asynchronous high resolution SAR ADCs is presented. In conventional SAR ADCs, the capacitive DAC size is growing exponentially with the converter resolution. The settling time of the MS ...

2017

A low-voltage CMOS-compatible time-domain photodetector, device & front end electronics

Denis Sallin

During the last decades, the usage of silicon photodetectors, both as stand-alone sensor or integrated in arrays, grew tremendously. They are now found in almost any application and any market range, from leisure products to high-end scientific apparatuses ...

EPFL2016

Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders

Alexios Konstantinos Balatsoukas Stimming

The goal of channel coding is to detect and correct errors that appear during the transmission of information. In the past few decades, channel coding has become an integral part of most communications standards as it improves the energy-efficiency of tran ...

EPFL2016

Approximation-aware Rewriting of AIGs for Error Tolerant Applications

Mathias Soeken

Approximation circuits offer superior performance (speed and area) compared to traditional circuits at the cost of computational accuracy. The accuracy of the results in approximation circuits is evaluated based on several error metrics such as worst-case ...

Assoc Computing Machinery2016