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Computer systems rely heavily on abstraction to manage the exponential growth of complexity across hardware and software. Due to practical considerations of compatibility between components of these complex systems across generations, developers have favou ...

The design of low-power wearables for the biomedical domain has received a lot of attention in recent decades, as technological advances in chip manufacturing have allowed real-time monitoring of patients using low-complexity ML within the mW range. Despit ...

The miniaturization of integrated circuits (ICs) and their higher performance and energy efficiency, combined with new machine learning algorithms and applications, have paved the way to intelligent, interconnected edge devices. In the medical domain, they ...

Modern hardware is increasingly complex, requiring increasing effort to understand in order to carefully engineer systems for optimal performance and effective utilization. Moreover, established design principles and assumptions are not portable to modern ...

Over the years, several clock and data recovery architectures have been proposed for wireless Amplitude Shift Keying (ASK) transmitted signals. State-of-the-art architectures mainly rely on synchronous phase-locked loop circuits or selfsampling systems, bo ...

The sense of touch can provide a robot with a wealth of information about the contact region when interacting with an unknown environment. Nevertheless, utilizing touch information to plan exploration paths and adjust robot posture to improve task efficien ...

Various forms of real-world data, such as social, financial, and biological networks, can be represented using graphs. An efficient method of analysing this type of data is to extract subgraph patterns, such as cliques, cycles, and motifs, from graphs. For ...

Accessing input data is a critical operation in data analytics: i) slow data access significantly degrades performance, and ii) storing everything in the fastest medium, i.e., memory, incurs high operational and hardware costs. Further, while GPUs offer in ...

Code-reuse attacks are dangerous threats that attracted the attention of the security community for years. These attacks aim at corrupting important control-flow transfers for taking control of a process without injecting code. Nowadays, the combinations o ...

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

Double-fetch bugs are a plague across all major operating system kernels. They occur when data is fetched twice across the user/kernel trust boundary while allowing concurrent modification. Such bugs enable an attacker to illegally access memory, cause den ...

The hardware complexity of modern machines makes the design of adequate programming models crucial for jointly ensuring performance, portability, and productivity in high-performance computing (HPC). Sequential task-based programming models paired with adv ...

Timely insights lead to business growth and scientific breakthroughs but require analytical engines that cope with the ever-increasing data processing needs. Analytical engines relied on rapid CPU improvements, yet the end of Dennard scaling stopped the fr ...

High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where ...

Model compression techniques have lead to a reduction of size and number of computations of Deep Learning models. However, techniques such as pruning mostly lack of a real co-optimization with hardware platforms. For instance, implementing unstructured pru ...

There is an increasing interest in a fast-growing machine learning technique called Federated Learning (FL), in which the model training is distributed over mobile user equipment (UEs), exploiting UEs' local computation and training data. Despite its advan ...

String sorting is a fundamental kernel of string matching and database index construction; yet, it has not been studied as extensively as fixed-length keys sorting. Because processing variable-length keys in hardware is challenging, it is no surprise that ...

The expeditious proliferation of Internet connectivity and the growing adoption of digital products have transformed various spheres of our everyday lives. This increased digitization of society has led to the emergence of new applications, which are deplo ...

Quantitative phase imaging (QPI) is an emerging label-free technique that produces images containing morphological and dynamical information without contrast agents. Unfortunately, the phase is wrapped in most imaging system. Phase unwrapping is the comput ...

Thread-Placement Learning

Chat with Graph Search

Secure Interface Design Leveraging Hardware/Software Support

BiomedBench: A benchmark suite of TinyML biomedical applications for low-power wearables

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Chaosity: Understanding Contemporary NUMA-architectures

An Ultra-Miniaturised CMOS Clock and Data Recovery System for Wireless ASK Transmission

Online active and dynamic object shape exploration with a multi-fingered robotic hand

Acceleration of graph pattern mining and applications to financial crime

HetCache: Synergising NVMe Storage and GPU acceleration for Memory-Efficient Analytics

WarpAttack: Bypassing CFI through Compiler-Introduced Double-Fetches

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis

Midas: Systematic Kernel TOCTTOU Protection

Decentralized in-order execution of a sequential task-based code for shared-memory architectures

Efficient Analytical Query Processing on CPU-GPU Hardware Platforms

From C/C plus plus Code to High-Performance Dataflow Circuits

Structured and tiled-based pruning of Deep Learning models targeting FPGA implementations

Federated Learning Over Wireless Networks: Convergence Analysis and Resource Allocation

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

Editorial

Architecture Exploration and Optimization of Heterogeneous Many-Core Compute and Memory Architectures with Architectural Extensions

Robust Phase Unwrapping via Deep Image Prior for Quantitative Phase Imaging