Publications related to Generating hardware and software for RISC-V cores generated with Rocket Chip generator

Related publications (20)

Formal Verification for Secure Processors: A Guide for Computer Architects

As computer architects continually push the limits of microarchitectural performance optimizations, securing hardware against speculative execution attacks feels like a Sisyphean task. This article explores the critical role computer architects can play in ...

IEEE COMPUTER SOC2024

The JPEG AI Standard: Providing Efficient Human and Machine Visual Data Consumption

Touradj Ebrahimi

The Joint Photographic Experts Group (JPEG) AI learning-based image coding system is an ongoing joint standardization effort between International Organization for Standardization (ISO), International Electrotechnical Commission (IEC), and International Te ...

IEEE COMPUTER SOC2023

Auto-Partitioning Heterogeneous Task-Parallel Programs with StreamBlocks

James Richard Larus, Seyedmahyar Emami

FPGAs play an increasing role in the reconfigurable accelerator landscape. A key challenge in designing FPGA-based systems is partitioning computation between processor cores and FPGAs. An appropriate division of labor is difficult to predict in advance an ...

ASSOC COMPUTING MACHINERY2022

tweedledum: A Compiler Companion for Quantum Computing

Giovanni De Micheli, Bruno Schmitt Antunes

This work presents tweedledum-an extensible open-source library aiming at narrowing the gap between high-level algorithms and physical devices by enhancing the expressive power of existing frameworks. For example, it allows designers to insert classical lo ...

IEEE2022

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

The ability of dataflow circuits to implement dynamic scheduling promises to overcome the conservatism of static scheduling techniques that high-level synthesis tools typically rely on. Yet, the same distributed control mechanism that allows dataflow circu ...

IEEE COMPUTER SOC2022

A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis

Giovanni Ansaloni

Approximate logic synthesis techniques have become popular in error-resilient systems, where accuracy requirements can be traded for improved energy efficiency. Many of these techniques operate on a circuit by substituting or removing some of its portions ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Flavio Ponzina, Marco Antonio Rios

The growing popularity of edge computing has fostered the development of diverse solutions to support Artificial Intelligence (AI) in energy-constrained devices. Nonetheless, comparatively few efforts have focused on the resiliency exhibited by AI workload ...

2022

Modernizing the NEURON Simulator for Sustainability, Portability, and Performance

Nicolas Pierre Jean Cornu, Alexandru Savulescu, Oliver James Lupton, Felix Schürmann, James Gonzalo King, Pramod Shivaji Kumbhar, Fernando Joaquim Leite Pereira, Omar Awile, Ioannis Magkanaris

The need for reproducible, credible, multiscale biological modeling has led to the development of standardized simulation platforms, such as the widely-used NEURON environment for computational neuroscience. Developing and maintaining NEURON over several d ...

2022

COCKTAIL: Multi-Core Co-Optimization Framework With Proactive Reliability Management

David Atienza Alonso, Marina Zapater Sancho, Ali Pahlevan, Darong Huang

High performance computing (HPC) servers aim to meet an increase in the number and complexity of tasks and, consequently, to address the energy efficiency challenge. In addition to energy efficiency, it is essential to manage lifetime limitations of power- ...

2022

Turning PathFinder Upside -Down: 1-4,xploring FPGA Switch -Blocks by Negotiating Switch Presence

Paolo Ienne, Stefan Nikolic

Automated switch-block exploration gains in importance as technology scaling brings more emphasis on the physical constraints, making it insufficient to rely on abstract measures of routability alone. In this work, we take an approach that significantly di ...

IEEE COMPUTER SOC2021

A 1-Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16-nm FinFET

Andreas Peter Burg, Robert Giterman, Adam Shmuel Teman

Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible embedded memory alternative to SRAM, offering higher density, lower leakage power consumption, and an inherent two-ported functionality. However, increased leakage currents and process variations und ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

The Cost of Scaling a Reliable Interconnection Topology

Rachid Guerraoui, Alexandre David Olivier Maurer

In distributed computing, many papers try to evaluate the message complexity of a distributed system as a function of the number of nodes n. But what about the cost of building the distributed system itself? Assuming that we want to reliably connect n node ...

2020

Accurate Emulation of Memristive Crossbar Arrays for In-Memory Computing

Irem Boybat Kara

In-memory computing is an emerging non-von Neumann computing paradigm where certain computational tasks are performed in memory by exploiting the physical attributes of the memory devices. Memristive devices such as phase-change memory (PCM), where informa ...

IEEE2020

LUT-Based Hierarchical Reversible Logic Synthesis

Giovanni De Micheli, Mathias Soeken

We present a synthesis framework to map logic networks into quantum circuits for quantum computing. The synthesis framework is based on lookup-table (urn networks, which play a key role in conventional logic synthesis. Establishing a connection between LUT ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Computational characteristics and hardware implications of brain tissue simulations

Francesco Cremonesi

Understanding the link between the brain's anatomy and its function through computer simulations of neural tissue models is a widely used approach in computational neuroscience. This technique enables rapid prototyping and testing of hypotheses, allowing r ...

EPFL2019

Hardware-conscious Query Processing in GPU-accelerated Analytical Engines

Anastasia Ailamaki, Periklis Chrysogelos, Panagiotis Sioulas

In order to improve their power efficiency and computational capacity, modern servers are adopting hardware accelerators, especially GPUs. Modern analytical DMBS engines have been highly optimized for multi-core multi-CPU query execution, but lack the nece ...

2019

Scaling Out Bioinformatics in the Data Center

Sam David Whitlock

Whole Genome Sequencing is a process in the field of bioinformatics that transforms biological samples of DNA into an electronic dataset of genetic bases. The process consists of two sequential components. First, the laboratory process of sequencing transf ...

EPFL2019

Abstracting Multi-Core Topologies with MCTOP

Rachid Guerraoui, Vasileios Trigonakis, Georgios Chatzopoulos

Portability and efficiency are usually antagonists in multi-core computing. In order to develop efficient code, one needs to take into account the topology of the target multi-cores (e.g., for locality). This clearly hampers code portability. In this paper ...

ACM Press2017

Automated Design Flow for Multi-Functional Dataflow-Based Platforms

Marco Mattavelli, Endri Bezati, Simone Casale Brunet

The implementation of processing platforms supporting multiple applications by runtime reconfigurations on dedicated hardware modules requires the solution of different problems. These problems are notably not-trivial since both platform and application co ...

Springer Verlag2015

Trinocular Adaptive Window Size Disparity Estimation Algorithm and Its Real-Time Hardware

Yusuf Leblebici, Alexandre Schmid, Raffaele Capoccia, Abdulkadir Akin, Jonathan Emmanuel D Narinx

This paper proposes a hardware-oriented trinocular adaptive window size disparity estimation (T-AWDE) algorithm and the first real-time trinocular disparity estimation (DE) hardware that targets high-resolution images with high-quality disparity results. T ...

2015