Tunnel FET with non-uniform gate capacitance for improved device and circuit level performance

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In this work, an AlGaN/GaN high electron mobility transistor (HEMT) with a large positive threshold voltage (VTH) is demonstrated, based on a digitally recessed barrier combined with a p-type NiO/SiO2 gate dielectric stack to form a recessed tri-junction HEMT (TJHEMT). Digital etching precisely recesses both the AlGaN barrier and sidewalls of the fins with nanometer-scale control, which combined with an additional depletion from p-type NiO/SiO2 gate dielectric stack, results in a VTH up to 1.5 V at 1 μA/mm.

Two-dimensional (2D) transition metal dichalcogenides (TMDCs) are promising materials for next-generation complementary metal-oxide-semiconductor (CMOS) technologies owing to their atomically thin channels and strong electrostatic control. Achieving the modulation of carrier polarity within a single material system is desirable for CMOS integration but remains challenging. Low-bandgap TMDCs could facilitate effective polarity tuning. Additionally, such materials provide a sensitive medium for probing doping

Disclosed is a diode device (1) including an insulator (7) extending between and in contact with two metal terminals (3, 5), wherein the insulator comprises at least one epsilon-near-zero (enz) material, or comprises at least one epsilon-negative (eng) material (7a) and a second insulator material (7b) forming a double insulator structure, and an electron source layer (9), particularly of graphene, between a metal terminal and the enz or eng material. the insulator provides a reduced effective capacitance w

This paper proposes a sub-nanoampere readout circuit designed for fast and precise detection with silicon nanowire (SiNW) memristive biosensors via voltage gap measurement. Compared to traditional solutions, the proposed circuit, completed in 65 nm bulk CMOS process, significantly enhances sensitivity to the picoampere range and reduces measurement time from several minutes to one second. Comprehensive performance evaluation has been performed by considering SiNW models with different crossing behavior, inc

The rising interest in robotics and virtual reality has driven a growing demand for intuitive interfaces that enable seamless human-robot interaction (HRI). Bio-signal-based solutions, using biopotential and bio-impedance, offer a promising approach for estimating human motion intention thanks to their ability to capture physiological neuromuscular activity in real time. This Review discusses the potential of biopotential and bio-impedance sensing systems for advancing HRI focusing on the role of integrated

Biosensors based on organic field-effect transistors can offer mechanical flexibility, stretchability and operational stability for conformal on-skin monitoring. However, bending, stretching, moisture and temperature changes can lead to signal artefacts and drifts. Here we report skin-like drift-free biosensors based on stretchable diode-connected organic field-effect transistors. Our approach relies on capacitive coupling and the subtraction of interference signals using two extended gates functionalized s

This directory contains the design files corresponding to the paper "AIPS: AI-Based Power Simulation for Pre-silicon Side-Channel Security Evaluation "(https://doi.org/10.5281/zenodo.18158825) by Ya Gao, Haocheng Ma, Tanchen Zhang, Jiaji He, Yiqiang Zhao, Mirjana Stojilovic, Yier Jin. The README file details the repository's structure, contents, and instructions for using the provided data. Abstract: Power side-channel analysis (SCA) attacks pose a significant threat to the security of integrated circuit

This work demonstrates dielectric elastomer actuators controlled by the world's first thin-film transistors on flexible substrate operating at 1kV, thereby enabling locally switching high-voltages on DEAs using a low control voltage. The high voltages required to drive DEAs limit their integration in complex systems, such as high resolution haptic displays and multiple-degree-of-freedom robotics. We report here a top-gate, thin-film transistor (TFT) with coplanar electrodes specifically designed to drive DE

Dual-edge-triggered (DET) synchronous operation is a very attractive option for low-power, high-performance designs. Compared to conventional single-edge synchronous systems, DET operation is capable of providing the same throughput at half the clock frequency. This can lead to significant power savings on the clock network that is often one of the major contributors to total system power. However, in order to implement DET operation, special registers need to be introduced that sample data on both clock-ed

3D-ICs based on TSV technology provide high bandwidth inter-chip connections. The drawback is that most of the existing TSVs consume a large amount of silicon real estate. We present circuit-level design and analysis of area efficient, low power, high-data-rate 3D serial TSV links. A design space exploration is performed and trade-offs in terms of area, power and performance are presented. Circuit simulations of RC-extracted layouts in 40nm CMOS-technology reveals that 8:1 serialization efficiently balances

This book discusses the opportunities offered by disruptive technologies to overcome the economical and physical limits currently faced by the electronics industry. It provides a new methodology for the fast evaluation of an emerging technology from an architectural perspective and discusses the implications from simple circuits to complex architectures. Several technologies are discussed, ranging from 3-D integration of devices (Phase Change Memories, Monolithic 3-D, Vertical NanoWires-based transistors) t

Silicon has been, and continues to be, the material support of integrated circuit (IC) technology-the enabling tool of one of the most impressive technological, industrial and social revolution of mankind. Silicon (both in monocrystalline and polycrystalline form as well as epitaxial silicon, silicon on insulator and silicon on nothing) has grown with IC technology for its ability to match the numerous and complex needs of microelectronics. In recent years, however, IC technology is experiencing problems of

This paper reports on the design and experimental verifications of a passive step-up rectifier for MEMS piezoelectric energy scavengers. The purpose of the proposed circuit is to improve system startup for vibration micro-generators without the need of an external source of energy. The design chosen is based on a voltage multiplier where conventional diodes are replaced by PMOS low-VT transistors. The circuit is produced in 1.8V 0.18μm UMC CMOS technology. Test and verifications were performed using a real

Designing spaces that are able to balance human comfort, energy-efficiency and well-being in a given climate is a real challenge, yet a problem faced every day by architects and building designers. Within the overall framework of promoting linkages between the engineering and design fields, this talk will discuss new approaches in research and education that are being developed to better integrate building performance considerations in the architectural design process. Daylighting is chosen as a strategic f

TID and displacement damage effects are studied for vertical and lateral power MOSFETs in five different technologies in view of the development of radiation-tolerant fully integrated DC-DC converters. Investigation is pushed to the very high level of radiation expected for an upgrade to the LHC experiments. TID induces threshold voltage shifts and, in n-channel transistors, source-drain leakage currents. Wide variability in the magnitude of these effects is observed. Displacement damage increases the on-re

Carbon nanotubes (CNTs) have been considered one of the most promising material to make nanodevices, in particular nanoelectromechanical systems (NEMS), due to their remarkable mechanical (Young's modulus ∼ 1 TPa) and electrical (high conductivity for metallic nanotubes) properties, nevertheless their low mass. Several NEMS device categories based on carbon nanotubes have been reported in the literature: sensors [1], non-volatile memories [2], tunable oscillators [3] and nanoswitches [4], which offer high s

This paper reports on an inductor fabrication method capable to deliver high quality factor (Q) and high self-resonance frequency (SRF) devices using quartz insulating substrates and thick high-conductivity copper lines. Inductors are key devices in RF circuits that, when fabricated on traditional semiconductor substrates, suffer from poor RF performances due to thin metallization and substrate related losses. Many previous works revealed that RF performances are strongly dependent on the limited metallizat

High defect density exhibited by nanoelectronic technologies, and parameter variability already affecting the operation of very-deep submicron CMOS systems demand for a combination of specific solutions, focusing at each various levels of abstraction in the development design-flow. Where traditionally applied methods fail under massive defect densities, we propose a top-down development strategy where the hardware overhead is adapted to the desired level of reliability. A CAD software tool supporting the me

A novel MEMS device architecture: the SOI SG-MOSFET, which combines a solid- state MOS transistor and a suspended metal membrane in a unique metal-over- gate architecture, is proposed. A unified physical analytical model (weak, moderate and strong inversions) is developed and used to investigate main electrostatic characteristics in order to provide first-order design criteria for low-voltage operation and high-performance. It is demonstrated that the use of a thin gate oxide (

Using a delta-doped GaAs/AlGaAs heterostructure with a 10 nm spacer layer, we exploit the metastable nature of the DX centers at low temperatures to control electrostatically their net frozen charge density. The concentration of DX(-) centers at 77 K is only determined by the applied gate voltage V-c during the cool-down of the sample to 77 K, i.e., it is independent, on the time scale of noise experiments, of the subsequent change in the gate bias V-GS. The sheet carrier concentration n(s) of the two-dimen

Tunnel FET with non-uniform gate capacitance for improved device and circuit level performance

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E-mode digitally recessed p-NiO tri-junction HEMT with V BR of 2.5 kV

Doping-Modulated Semiconductor-to-Metal Transformation in a Low-Band-Gap Two-Dimensional Material

Metal-insulator-metal tunnelling diode for operation in the visible or infrared spectrum

3.3V Sub-nA Voltage Gap Readout Circuit for Memristive Biosensing in Silicon Nanowire

Using Biopotential and Bio-impedance for Intuitive Human-robot Interaction

Skin-like drift-free biosensors with stretchable diode-connected organic field-effect transistors

AIPS: AI-Based Power Simulation for Pre-silicon Side-Channel Security Evaluation

Flexible 1kV thin-film transistor driving out-of-plane dielectric elastomer actuator

An Overlap-Contention Free True-Single-Phase Clock Dual-Edge-Triggered Flip-Flop

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Disruptive Logic Architectures and Technologies

Nanoengineered Silicon: Technology and Applications

A Sub-Threshold Passive Step-Up Rectifier for Vibration Energy Scavengers

Performance at the service of architecture

TID and Displacement Damage Effects in Vertical and Lateral Power MOSFETs for Integrated DC-DC Converters

RF NEM capacitive switch based on dense horizontal arrays of CNTs

High quality factor copper inductors integrated in deep dry-etched quartz substrates

Design for Reliability of Nanometer-Scale Electronics under High Defect Density

Modeling and design of a low-voltage SOI suspended-gate MOSFET (SG- MOSFET) with a metal-over-gate architecture

Evidence for screening effects on the 1/f current noise in GaAs/AlGaAs modulation doped field effect transistors