Design and analysis techniques for dynamic current mirrors

Today's world of electronics becomes more and more digital and therefore CMOS becomes the dominant technology. A CMOS process compared to a bipolar process offers several advantages, mainly a low power consumption which is important for portable systems powered by batteries or for large systems. Another point is the smaller device geometries, which increase the number of gates that can be packed on a single chip. Parallel to the increasing digital domain the analog field persists, because the origin of physical phenomenons and their perception is analog. Electronic sensors perceive these analog events and deliver a corresponding output signal. If this analog signal is not suitable for digital processing some analog preconditioning must be done [YEN82]. Combining both types of signal processing on the same chip to obtain the best possible performances is therefore desirable [MID84]. CMOS technology has led to a wide use of voltages and charge transfers for signal processing. As the feature sizes shrink a lower supply voltage is imposed, which reduces the dynamic voltage range of the circuits. Because process parameters are chosen to optimize digital performances, the analog functional blocks have to adapt themselves to the restricted voltage range. Current mode circuits offer a solution to these problems as they require only a baseline digital process and avoid many of the anticipated low voltage problems by operating in the current domain [HUG89]. Due to the non-linear current-voltage relationship the dynamic range of current-mode signals is larger than that of voltage-mode signals. Therefore the current mode approach can provide attractive and elegant solutions for many circuit and system problems [TOU90]. A ubiquitous elementary building block in most analog integrated circuits is the current mirror which is able to multiply and duplicate an imposed input current, that contains the information (bias or signal). The reproduced output current of is then available for any subsequent processing. Unfortunately, due to random process variations, transistor parameters are affected by a certain variation of the transconductance parameter and of the threshold voltage [SHY84], [LAK86]. Hence, the output currents of transistors which have been designed identically are different. These random variations, the so-called devices mismatch, are a major limitation for most accurate and precise current mode circuit applications. Another main limitation of CMOS circuits is the 1/f flicker noise of the MOS transistors. The standard technique to reduce this 1/f noise and the error due to mismatch is to increase the transistor area and to overwhelm the threshold mismatch with a high gate voltage overhead, which simultaneously increases the saturation voltage of the devices. The performance of a mirror with low saturation voltage can be improved by using lateral bipolar transistors [VIT83]. The resulting current error can be lower than 1%, but the major handicap is th