Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures

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Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines

Marco Mattavelli, Anatoly Prihozhy, Endri Bezati, Simone Casale Brunet

Large dataflow designs appear as a result of functional specification of modern complex digital systems and/ or a result of unfolding and behavioral transformation of looped and branched programs. Since deep-submicron silicon technology provides large amou ...

IEEE2018

Scalable Synchronization in Shared-Memory Systems: Extrapolating, Adapting, Tuning

Georgios Chatzopoulos

As hardware evolves, so do the needs of applications. To increase the performance of an application, there exist two well-known approaches. These are scaling up an application, using a larger multi-core platform, or scaling out, by distributing work to mul ...

EPFL2018

Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms

Marco Mattavelli, Endri Bezati, Simone Casale Brunet, Malgorzata Maria Michalska

Executing a dataflow program on a parallel platform requires assigning to each buffer a given size so that correct program executions take place without introducing any deadlock. Furthermore, in the case of dynamic dataflow programs, specific buffer size a ...

2017

Performance estimation of program partitions on multi-core platforms, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

Marco Mattavelli, Junaid Jameel Ahmad, Endri Bezati, Simone Casale Brunet, Malgorzata Maria Michalska

The exploration of different design configurations of dynamic dataflow programs executed on many-core or multi-core platforms is, in general, a very difficult task. Determining a close-to-optimal partitioning, scheduling and buffer dimensioning configurati ...

2017

Systematic Design Space Exploration of Dynamic Dataflow Programs for Multi-core Platforms

Malgorzata Maria Michalska

The limitations of clock frequency and power dissipation of deep sub-micron CMOS technology have led to the development of massively parallel computing platforms. They consist of dozens or hundreds of processing units and offer a high degree of parallelism ...

EPFL2017

Near-optimal Deployment of Dataflow Applications on Many-core Platforms with Real-time Guarantees

Alena Simalatsar, Stefanos Skalistis

Safe and optimal deployment of data-streaming applications on many-core platforms requires the realistic estimation of task Worst-Case Execution Time (WCET). On the other hand, task WCET depends on the deployment solution, due to the varying number of inte ...

IEEE2017

Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures

Marco Mattavelli, Nicolas Zufferey, Endri Bezati, Malgorzata Maria Michalska

The implementations of signal processing systems on the emerging many-core or multi-core processing platforms require to solve a very difficult problem: how to partition and schedule the processing tasks according to given optimization functions such as da ...

2016

High-Precision Performance Estimation of Dynamic Dataflow Programs

Marco Mattavelli, Endri Bezati, Simone Casale Brunet, Malgorzata Maria Michalska

An important challenge for a dataflow designer is to efficiently explore the design space in order to find a set of configurations that satisfy the defined objective function. The exploration directions may involve the partitioning, scheduling and buffer d ...

2016

Performance Estimation Based Multicriteria Partitioning Approach for Dynamic Dataflow Programs

Marco Mattavelli, Nicolas Zufferey, Malgorzata Maria Michalska

The problem of partitioning a dataflow program onto a target architecture is a difficult challenge for any application design. In general, since the problem is NP-complete, it consists of looking for high quality solutions in terms of maximizing the achiev ...

Hindawi Limited2016

High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms

Marco Mattavelli, Endri Bezati, Simone Casale Brunet

The growing complexity of digital signal processing applications make a compelling case the use of high-level design and synthesis methodologies for the implementation on programmable logic devices and embedded processors. Past research has shown that, for ...

2016

Programming Models and Methods for Heterogeneous Parallel Embedded Systems

Marco Mattavelli, Endri Bezati, Simone Casale Brunet

The growing complexity of digital signal processing applications makes a compelling case for the adoption of higher-level programming models such as dataflow for the implementation of applications on programmable logic devices and many/multi-core embedded ...

2016

High-level system synthesis and optimization of dataflow programs for MPSoCs

Marco Mattavelli, Endri Bezati, Simone Casale Brunet

The growing complexity of digital signal processing applications make a compelling case the use of high-level design and synthesis methodologies for the implementation on reconfigurable and embedded devices. Past research has shown that raising the level o ...

2016

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