Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures

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Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...

Dataflow programming is a methodology that enables the development of high-level, parametric programs that are independent of the underlying platform. This approach is particularly useful for heterogeneous platforms, as it eliminates the need to rewrite ap ...

The demise of Moore's Law and Dennard Scaling has revived interest in specialized computer architectures and accelerators. Verification and testing of this hardware depend heavily upon cycle-accurate simulation of register-transfer-level (RTL) designs. The ...

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

When applications have unpredictable memory accesses or irregular control flow, dataflow circuits overcome the limitations of statically scheduled high-level synthesis (HLS). If memory dependences cannot be determined at compile time, dataflow circuits rel ...

With FPGAs facing broader application domains, the conversion of imperative languages into dataflow circuits has been recently revamped as a way to overcome the conservatism of statically scheduled high-level synthesis. Apart from the ability to extract pa ...

In recent years, the number and variety of heterogeneous multiprocessor system-on-chip MPSoCs, such as for instance Zynq platforms, has sensibly increased. However, today all design flow solutions capable of programming the different components of such pla ...

The capability to process high-resolution videos in real-time is becoming more important in a wide variety of applications such as autonomous vehicles, virtual reality or intelligent surveillance systems. The high-accuracy and complex video processing algo ...

The implementation and optimization of dynamic dataflow programs on multi/many-core platforms require solving a very difficult problem: how to partition and schedule the processing elements and dimension their interconnecting buffers according to given opt ...

Writing and optimizing application software for heterogeneous platforms including GPU units is a very difficult task that requires designer efforts and resources to consider several key elements to obtain good performance. Dataflow programming has shown to ...

The paper introduces and specifies a formalism that provides complete representations of dataflow process network (DPN) program executions, by means of directed acyclic graphs. Such graphs, also known as execution trace graphs (ETG), are composed of nodes ...

The performance of programs executed on heterogeneous parallel platforms largely depends on the design choices regarding how to partition the processing on the various different processing units. In other words, it depends on the assumptions and parameters ...

This paper presents shared-variable synchronization approaches for dataflow programming. The mechanisms do not require any substantial model of computation (MoC) modification, and is portable across both for hardware (HW) and software (SW) low-level code s ...

Recent GPU architectures make available numbers of parallel processing units that exceed by orders of magnitude the ones offered by CPU architectures. Whereas programs written using dataflow programming languages are well suited for programming heterogeneo ...

The performance of programs written in languages following the dataflow model of computation (MoC) largely depends on the configuration (partitioning, mapping, scheduling, buffer dimensioning) chosen during the synthesis stages. Furthermore, this programmi ...

The design of new streaming systems is becoming a major area of research to deploy services targeted in the Internet-of-Things (IoT) era. In this context, the new High Efficiency Video Coding (HEVC) standard provides high efficiency and scalability of qual ...

Large dataflow designs appear as a result of functional specification of modern complex digital systems and/ or a result of unfolding and behavioral transformation of looped and branched programs. Since deep-submicron silicon technology provides large amou ...

High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. These tools almost universally build datapaths that are controlled using a centralized controller which relies on a static, compile-time schedule to determine ...

As hardware evolves, so do the needs of applications. To increase the performance of an application, there exist two well-known approaches. These are scaling up an application, using a larger multi-core platform, or scaling out, by distributing work to mul ...

Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures

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Highly Parallel RTL Simulation

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System

Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs

Speculative Dataflow Circuits

An Heterogeneous Compiler Of Dataflow Programs For Zynq Platforms

A Real-Time Multi-Camera Depth Estimation ASIC with Custom On-Chip Embedded DRAM

High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Execution Trace Graph of Dataflow Process Networks

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network Execution

Shared-variable Synchronization Approaches for Dynamic Data Flow Programs

Inter-actions parallel execution on GPU from high-level dataflow synthesis

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms

A Machine Learning-Based Strategy for Efficient Resource Management of Video Encoding on Heterogeneous MPSoCs

Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines

High-Level Synthesis of Dynamically Scheduled Circuits

Scalable Synchronization in Shared-Memory Systems: Extrapolating, Adapting, Tuning