A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18um CMOS technology

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This article presents a two-times interleaved, loop-unrolled SAR analog-to-digital converter (ADC) operational from 300 down to 4.2 K. The 6-8-bit resolution and the sampling speed up to 1 GS/s are targeted at digitizing the multi-channel frequency-multipl ...

The vibrational response of solid materials and structural components is substantially governed by their mechanical and geometrical properties. Low-frequency vibrations and modal frequencies are sensitive to global geometrical deviations, while high-freque ...

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This paper presents a low-power single-channel 8-bit loop-unrolled (LU) successive approximation register (SAR) analog-to-digital-converter (ADC) with a novel common-mode adaptive background comparator offset calibration scheme. LU-SAR ADCs use multiple co ...

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The aim of this thesis is to implement, analyze and improve the selected low noise clock generation and distribution techniques for ADC implementations. The thesis is divided into two parts. The first part focuses on the sampling phase generation and distr ...

Sampling has always been at the heart of signal processing providing a bridge between the analogue world and discrete representations of it, as our ability to process data in continuous space is quite limited. Furthermore, sampling plays a key part in unde ...

With the advent of intelligent sensor nodes in everyday life, low power aspects of system design become more and more important. Adaptive body biasing is a promising methodology to achieve dynamic adaptation of the tradeoff between performance and energy b ...

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Finite rate of innovation (FRI) is a powerful reconstruction framework enabling the recovery of sparse Dirac streams from uniform low-pass filtered samples. An extension of this framework, called generalised FRI (genFRI), has been recently proposed for han ...

This paper presents a 9-bit 222 MS/s low-power asynchronous single-bit/cycle successive approximation register (SAR) ADC. The SAR ADC combines techniques such as asynchronous clocking, binary-weighted custom-designed capacitive DAC with small unit capacito ...

Sampling is classically performed by recording the amplitude of the input at given time instants; however, sampling and reconstructing a signal using multiple devices in parallel becomes a more difficult problem to solve when the devices have an unknown sh ...

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Emerging technologies such as plasmonics and photonics are promising alternatives to CMOS for high throughput applications, thanks to their waveguide's low power consumption and high speed of computation. Besides these qualities, these novel technologies a ...

The benefits and limitations inherent to the 2D post-processing of measurements from Brillouin optical time-domain analyzers are investigated from a fundamental point of view. In a preliminary step, the impact of curve fitting on the precision of the estim ...

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In this paper a continuous-time low-pass analog filter based on the Cascoded Super Source Follower (C-SSF) architecture, implemented in a 28-nm bulk CMOS process, is presented. The target application is the transceiver analog baseband for the next-generati ...

The dissipated energy (Ediss) related to the resonant charging/discharging of a transistor output capacitance, becomes a dominant loss factor for power converters operating in the MHz range. A recent work has introduced a small-signal measurement method to ...

A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18um CMOS technology

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