Publications related to Improving Standard-Cell Design Flow using Factored Form Optimization

Related publications (10)

Algebraic and Boolean Methods for SFQ Superconducting Circuits

Giovanni De Micheli, Alessandro Tempia Calvino

Rapid single-flux quantum (RSFQ) is one of the most advanced and promising superconducting logic families, offering exceptional energy efficiency and speed. RSFQ technology requires delay registers (DFFs) and splitter cells to satisfy the path-balancing an ...

2024

Strange Loops in Design and Technology: 59th DAC Keynote Speech

Giovanni De Micheli

This keynote paper highlights the interaction between emerging technologies and software tools to enable the current evolution of electronic design automation systems. ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2023

Design and Optimization of Quantum Electronic Circuits

Giovanni De Micheli

Quantum electronic circuits where the logic information is processed and stored in single flux quanta promise efficient computation in a performance/power metric, and thus are of utmost interest as possible replacement or enhancement of CMOS. Several elect ...

ASSOC COMPUTING MACHINERY2022

Tunneling Current Through a Double Quantum Dots System

Jean-Michel Sallese, Farzan Jazaeri

Electrostatically confined quantum dots in semiconductors hold the promise to achieve high scalability and reliability levels for practical implementation of solid-state qubits where the electrochemical potentials of each quantum dot can be independently c ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies

Giovanni De Micheli, Heinz Riener, Akash Kumar

Emerging reconfigurable nanotechnologies allow the implementation of self-dual functions with a fewer number of transistors as compared to traditional CMOS technologies. To achieve better area results for Reconfigurable Field-Effect Transistors (RFET)-base ...

IEEE2021

Designing a DDS-Based SoC for High-Fidelity Multi-Qubit Control

Edoardo Charbon

The design of a large-scale quantum computer requires co-optimization of both the quantum bits (qubits) and their control electronics. This work presents the first systematic design of such a controller to simultaneously and accurately manipulate the state ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Hassan Ghasemzadeh Mohammadi

Controllable-Polarity Silicon Nanowire Transistors (CP-SiNWFETs) are among the promising candidates to complement or even replace the current CMOS technology in the near future. Polarity control is a desirable property that allows the on-line configuration ...

Institute of Electrical and Electronics Engineers2015

Top-Down Fabrication of Gate-All-Around Vertically-Stacked Silicon Nanowire FETs with Controllable Polarity

Giovanni De Micheli, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Davide Sacchetto, Jian Zhang, Michele De Marchi

Asthe currentMOSFET scaling trend is facing strong limitations, technologies exploiting novel degrees of freedom at physical and architecture level are promising candidates to enable the continuation of Moore's predictions. In this paper, we report on the ...

Institute of Electrical and Electronics Engineers2014

Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design

Yusuf Leblebici, Seyed Armin Tajalli

The large subthreshold leakage current of static CMOS logic circuits designed in modern nanometer-scale technologies is one of the main barriers for implementing ultra-low power digital systems. Subthreshold source-coupled logic (STSCL) circuits are based ...

IEEE2009

Fault-Tolerant Logic Gates Using Neuromorphic CMOS Circuits

Yusuf Leblebici, Alexandre Schmid, Neil Joye

Fault-tolerant design methods for VLSI circuits, which have traditionally been addressed at system level, will not be adequate for future very-deep submicron CMOS devices where serious degradation of reliability is expected. Therefore, a new design approac ...

IEEE2007