Alexandre Sébastien Julien Willommet

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Energy efficiency remains a challenge for the design of non-volatile resistive memories (ReRAMs) arrays. This memory technology suffers from intrinsic variability in switching speed, programming voltages and resistance levels. The programming conditions of ...

Deeply-scaled three-dimensional (3D) Multi-Processor Systems-on-Chip (MPSoCs) enable high performance and massive communication bandwidth for next-generation computing. However, as process nodes shrink, temperature-dependent leakage dramatically increases, ...

Compute memories are memory arrays augmented with dedicated logic to support arithmetic. They support the efficient execution of data-centric computing patterns, such as those characterizing Artificial Intelligence (AI) algorithms. These architectures can ...

Analog in-memory computing (AIMC) cores offers significant performance and energy benefits for neural network inference with respect to digital logic (e.g., CPUs). AIMCs accelerate matrix-vector multiplications, which dominate these applications’ run-time. ...

With the spread of cloud services and Internet of Things concept, there is a popularization of machine learning and artificial intelligence based analytics in our everyday life. However, an efficient deployment of these data-intensive services requires per ...

The growing popularity of edgeAI requires novel solutions to support the deployment of compute-intense algorithms in embedded devices. In this article, we advocate for a holistic approach, where application-level transformations are jointly conceived with ...

The increasing ubiquity of edge devices in the consumer market, along with their ever more computationally expensive workloads, necessitate corresponding increases in computing power to support such workloads. In-memory computing is attractive in edge devi ...

Resistive switching memory technologies (RRAM) are seen by most of the scientific community as an enabler for Edge-level applications such as embedded deep Learning, AI or signal processing of audio and video signals. However, going beyond a "simple'' repl ...

The growing popularity of edge computing has fostered the development of diverse solutions to support Artificial Intelligence (AI) in energy-constrained devices. Nonetheless, comparatively few efforts have focused on the resiliency exhibited by AI workload ...

Flow Cell Arrays (FCA) technology employs microchannels filled with an electrolytic fluid to concurrently provide cooling and power generation to integrated circuits (ICs). This solution is particularly appealing for Three-Dimensional Multi-Processor Syste ...

By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the array periphery, arithmetic operations are then derived with little additional o ...

The ever-increasing computational complexity and energy consumption of today's applications, such as Machine Learning (ML) algorithms, not only strain the capabilities of the underlying hardware but also significantly restrict their wide deployment at the ...

The increasing size of Convolutional Neural Networks (CNNs) and the high computational workload required for inference pose major challenges for their deployment on resource-constrained edge devices. In this paper, we address them by proposing a novel In-M ...

The growing need for connected, smart and energy efficient devices requires them to provide both ultra-low standby power and relatively high computing capabilities when awoken. In this context, emerging resistive memory technologies (RRAM) appear as a prom ...

Integrated Flow Cell Array (FCA) technology promises to address the power delivery and heat dissipation challenges in three-dimensional Multi Processor Systems-on-Chips (3D MPSoCs) by providing combined inter-tier liquid cooling and power generation capabi ...

As more and more high density memories are required to satisfy the Internet of Things ecosystem, academics and industrials are looking for an intermediate solution to fill the gap between DRAM and Flash NAND in the memory hierarchy. The emergence of Resist ...

Hybrid caches consisting of both SRAM and emerging Non-Volatile Random Access Memory (eNVRAM) bitcells increase cache capacity and reduce power consumption by taking advantage of eNVRAM's small area footprint and low leakage energy. However, they also inhe ...

Event-based sensors have the potential to optimize energy consumption at every stage in the signal processing pipeline, including data acquisition, transmission, processing, and storage. However, almost all state-of-the-art systems are still built upon th ...

In-Memory Computing (IMC) solutions, and particularly bitline computing in SRAM, appear promising as they mitigate one of the most energy consuming aspects in computation: data movement. In this work we propose a fast (2.4Ghz for bitwise operations and 2.4 ...

Alexandre Sébastien Julien Willommet

Chat with Graph Search

Switching event detection and self-termination programming circuit for energy efficient ReRAM memory arrays

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

Overflow-free compute memories for edge AI acceleration

ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication

A hardware/software co-design vision for deep learning at the edge

BLADE: A BitLine Accelerator for Devices on the Edge

Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge

Thermal and Power-Aware Run-Time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs

Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing

RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures

A Design Framework for Thermal-Aware Power Delivery Network in 3D MPSoCs with Integrated Flow Cell Arrays

Overflow-free Compute Memories for Edge AI Acceleration

RRAM Crossbar Arrays for Storage Class Memory Applications : Throughput and Density Considerations

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

An Error-Based Approximation Sensing Circuit for Event-Triggered Low-Power Wearable Sensors

A Fast, Reliable and Wide-voltage-range In-memory Computing Architecture