Publications by Heinz Riener | EPFL Graph Search

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This article proposes a new logic synthesis and verification paradigm based on circuit simulation. In this paradigm, high quality, expressive simulation patterns are pregenerated to be reused in multiple runs of optimization and verification algorithms, re ...

Majority-inverter graphs (MIGs) are a logic representation with remarkable algebraic and Boolean properties that enable efficient logic optimizations beyond the capabilities of traditional logic representations. Further, since many nano-emerging technologi ...

Most logic synthesis algorithms work on graph representations of logic functions with nodes associated with arbitrary logic expressions or simple logic functions and iteratively optimize such graphs. While recent multilevel logic synthesis efforts focused ...

Individual transistors based on emerging reconfigurable nanotechnologies exhibit electrical conduction for both types of charge carriers. These transistors (referred to as Reconfigurable Field-Effect Transistors (RFETs)) enable dynamic reconfiguration to d ...

Emerging reconfigurable nanotechnologies allow the implementation of self-dual functions with a fewer number of transistors as compared to traditional CMOS technologies. To achieve better area results for Reconfigurable Field-Effect Transistors (RFET)-base ...

Adiabatic quantum-flux-parametron (AQFP) circuits are a family of superconducting electronic (SCE) circuits that have recently gained growing interest due to their low-energy consumption, and may serve as alternative technology to overcome the down-scaling ...

We present an exact approach to synthesize temporal-logic formulas in linear temporal logic (LTL) from a set of given positive and negative example traces. Our approach uses topology structures, in particular partial DAGs, to partition the search space int ...

Medical cyber-physical systems are a new trend of software controlled physical systems that are increasingly common in medical domains. With rapid developments in medical science and computer technology, safety verification and simulation becomes more chal ...

Most quantum algorithms assume some specific initial state in superposition of basis states before performing the desired application-specific computations. The preparation of such states itself requires a computation performed by a quantum circuit. In thi ...

We propose a flow for automated quantum compila- tion. Our flow takes a Boolean function implemented in Python as input and translates it into a format appropriate for reversible logic synthesis. We focus on two quantum compilation tasks: uniform state pre ...

We present an outline of the field of Design Understanding and summarize state-of-the-art research in deriving human-understandable knowledge in form of logic properties from an unknown design. ...

The behavioral revisions to the design are frequent in the late stage of the semiconductor chip development. Quite often, their realization emphasizes incrementality that seeks minimum perturbation of the existing implementation. This tutorial paper poses ...

Logic synthesis is a fundamental step in the realization of modern integrated circuits. It has traditionally been employed for the optimization of CMOS-based designs, as well as for emerging technologies and quantum computing. Recently, it found applicatio ...

The problem of generating a minimal implementation of a given Boolean function is called exact synthesis. The parameter to be minimized is often the total number of gates used for the implementation. The exact synthesis engine is considered an essential to ...

This paper proposes a versatile mapping approach that has three objectives: i) it can map from one technology-independent graph representation to another; ii) it can map to a cell library; iii) it supports logic rewriting. The method is cut-based, mitigate ...

Adiabatic quantum-flux parametron (AQFP) is an energy-efficient superconducting technology. Buffer and splitter (B/S) cells must be inserted to an AQFP circuit to meet the technology-imposed constraints on path balancing and fanout branching. These cells a ...

The paper presents a generalization of DAG-aware AIG rewriting for k-feasible Boolean networks, whose nodes are k-input lookup tables (k-LUTs). We introduce a high-effort DAG-aware rewriting algorithm, called cut rewriting, which uses exact synthesis to co ...

Heinz Riener

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A Simulation-Guided Paradigm for Logic Synthesis and Verification

Size Optimization of MIGs with an Application to QCA and STMG Technologies

Three-Input Gates for Logic Synthesis

Utilizing XMG-based Synthesis to Preserve Self-Duality for RFET-Based Circuits

Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits

Exact Synthesis of LTL Properties from Traces

Generating Safety Guidance for Medical Injection with Three-Compartment Pharmacokinetics Model

Automatic Uniform Quantum State Preparation Using Decision Diagrams

From Boolean functions to quantum circuits: A scalable quantum compilation flow in C++

Design Understanding: From Logic to Specification

Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks

Revisiting Explicit Enumeration for Exact Synthesis

A Versatile Mapping Approach for Technology Mapping and Graph Optimization

Beyond Local Optimality of Buffer and Splitter Insertion for AQFP Circuits

On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis

Three-Input Gates for Logic Synthesis

External Don’t Cares in Logic Synthesis

Scalable Generic Logic Synthesis: One Approach to Rule Them All