Heinz Riener

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Related publications (29)

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Scalable Generic Logic Synthesis: One Approach to Rule Them All

Mathias Soeken, Heinz Riener, Eleonora Testa, Luca Gaetano Amarù, Winston Jason Haaswijk, Giovanni De Michele

ACM2019

Logic Optimization of Majority-Inverter Graphs

Giovanni De Micheli, Mathias Soeken, Heinz Riener, Eleonora Testa, Luca Gaetano Amarù, Winston Jason Haaswijk

Majority-inverter graphs (MIGs) are a multi-level logic representation of Boolean functions with remarkable algebraic and Boolean properties that enable efficient logic optimizations beyond the capabilities of conventional logic representations. In this pa ...

VDE Verlag2019

Exact DAG-Aware Rewriting

Mathias Soeken, Heinz Riener

We present a generic resynthesis framework for optimizing Boolean networks parameterized with a multi-level logic representation, a cut-computation algorithm, and a resynthesis algorithm. The framework allows us to realize powerful optimization algorithms ...

IEEE2020

Synthesizing adaptive test strategies from temporal logic specifications

Heinz Riener

Springer2019

Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition

Giovanni De Micheli, Heinz Riener, Siang-Yun Lee

Logic resynthesis is the problem of finding a dependency function to re-express a given Boolean function in terms of a given set of divisor functions. In this paper, we study logic resynthesis of majority-based circuits, which is motivated by the increasin ...

IEEE2021

Evaluating ESOP Optimization Methods in Quantum Compilation Flows

Giovanni De Micheli, Heinz Riener, Bruno Schmitt Antunes, Giulia Meuli

Springer2019

Boolean Rewriting Strikes Back: Reconvergence- Driven Windowing meets Resynthesis

Giovanni De Micheli, Heinz Riener, Siang-Yun Lee

The paper presents a novel DAG-aware Boolean rewriting algorithm for restructuring combinational logic before technology mapping. The algorithm, called window rewriting, repeatedly selects small parts of the logic and replaces them with more compact implem ...

IEEE2022

Customizable On-the-fly Design Space Exploration for Logic Optimization of Emerging Technologies

Giovanni De Micheli, Heinz Riener, Siang-Yun Lee

2023

An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications

Giovanni De Micheli, Heinz Riener, Siang-Yun Lee

2022