Publications by Andrea Guerrieri

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Dynamically scheduled high-level synthesis can exploit high levels of parallelism in poorly-predictable control-dominated applications. Yet, dataflow circuits are often generated by literal conversion of basic blocks into circuits interconnected in such a ...

High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where ...

High-level synthesis (HLS) is the process of automatically generating circuits out of high-level language descriptions. Previous research has shown that dynamically scheduled HLS through elastic circuit generation is successful at exploiting parallelism in ...

High-level synthesis is a mature Electronics Design Automation (EDA) technology for building hardware design in a short time. It produces automatically HDL code for FPGAs out of C/C++, bridging the gap from algorithm to hardware. Nevertheless, sometimes th ...

When applications have unpredictable memory accesses or irregular control flow, dataflow circuits overcome the limitations of statically scheduled high-level synthesis (HLS). If memory dependences cannot be determined at compile time, dataflow circuits rel ...

FPGAs (Field Programmable Gate Array) are an attractive technology for high-speed data processing in space missions due to their unbeatable flexibility and best performance-to-power ratio in comparison to software. However FPGAs suffer from 3 major drawbac ...

Since their inception more than thirty years ago, field-programmable gate arrays (FPGAs) have been widely used to implement a myriad of applications from different domains. As a result of their low-level hardware reconfigurability, FPGAs have much faster d ...

Due to increased embedded processing requirements, modern SoCs are becoming heterogeneous computing platforms by combining traditional processing units with custom reconfigurable hardware accelerators (HAs) on an FPGA fabric. However, efficiently managing ...

With FPGAs facing broader application domains, the conversion of imperative languages into dataflow circuits has been recently revamped as a way to overcome the conservatism of statically scheduled high-level synthesis. Apart from the ability to extract pa ...

To achieve resource-efficient hardware designs, high-level synthesis (HLS) tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed in conjunction with operation scheduling to ensure th ...

We use the S-matrix bootstrap to carve out the space of unitary, analytic, crossing symmetric and supersymmetric graviton scattering amplitudes in nine, ten and eleven dimensions. We extend and improve the numerical methods of our previous work in ten dime ...

Dynamically scheduled HLS, through dataflow circuit generation, has proven successful at exploiting operation-level parallelism in several important situations where statically scheduled HLS fails. Yet, although existing dataflow circuits support out-of-or ...

Dataflow circuits promise to overcome the scheduling limitations of standard HLS solutions. However, their performance suffers due to timing overheads caused by their handshake communication protocol. Current pipelining solutions fail to account for logic ...

To achieve resource-efficient hardware designs, HLS tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed together with operation scheduling to ensure the best possible unit usage at ...

High-level synthesis (HLS) tools generate hardware designs from high-level software languages while sidestepping intricate low-level hardware details. However, HLS tools struggle with precise dynamic power estimation and optimization: the high abstraction ...

The ability of dataflow circuits to implement dynamic scheduling promises to overcome the conservatism of static scheduling techniques that high-level synthesis tools typically rely on. Yet, the same distributed control mechanism that allows dataflow circu ...

Numerical data for scattering amplitudes of Goldstone bosons in d=4 obtained by solving various optimisation problems. The data is stored in .m files. Mathematica notebook is provided for loading and plotting the data. ...

High-level synthesis tools, both commercial and academic, typically rely on static scheduling to produce high-throughput pipelines. However, in applications with unpredictable memory accesses or irregular control flow, these tools need to make pessimistic ...

In this work, we present an automated approach for locating power-wasting attackers in shared FPGAs. In this approach, the FPGA shell is responsible for, first, placing the user designs and, second, inserting voltage sensors in a nonintrusive and adaptive ...

FPGAs hold great promises for Post-Quantum Cryptography (PQC) hardware through the adoption of electronic design automation tools such as High-Level Synthesis (HLS). Previous works demonstrated how the combination of pragmas and code refactoring techniques ...

Andrea Guerrieri

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Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits

From C/C plus plus Code to High-Performance Dataflow Circuits

Unleashing Parallelism in Elastic Circuits with Faster Token Delivery

Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level Synthesis

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs

A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing

Synthesizing General-Purpose Code Into Dynamically Scheduled Circuits

Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips

Speculative Dataflow Circuits

Resource Sharing in Dataflow Circuits

Where is M-theory in the space of scattering amplitudes?

Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits

An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits

Resource Sharing in Dataflow Circuits

Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits

Numerical data for scattering amplitudes of Neutral Goldstone bosons in 4d

Invited Tutorial Dynamatic: From C/C plus plus to Dynamically Scheduled Circuits

Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs

Blending Scheduling Barriers: A Hybrid Approach for FPGA-based Post-Quantum Cryptography