Publications by James Richard Larus

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Trusted Execution Environments (TEEs), such as Intel SGX enclaves, use hardware to ensure the confidentiality and integrity of operations on sensitive data. While the technology is available on many processors, the complexity of its programming model and i ...

Side-channel attacks allow adversaries to infer sensitive information from non-functional characteristics. Prior side-channel detection work is able to identify numerous potential vulnerabilities. However, in practice, many such vulnerabilities leak a negl ...

Programming languages and systems have failed to address the security implications of the increasingly frequent use of public libraries to construct modern software. Most languages provide tools and online repositories to publish, import, and use libraries ...

Non-Volatile Memory offers the possibility of implementing high-performance, durable data structures. However, achieving performance comparable to well-designed data structures in non-persistent (transient) memory is difficult, primarily because of the cos ...

The demise of Moore's Law and Dennard Scaling has revived interest in specialized computer architectures and accelerators. Verification and testing of this hardware depend heavily upon cycle-accurate simulation of register-transfer-level (RTL) designs. The ...

Dynamic program slicing can significantly reduce the amount of code developers need to inspect by focusing only on program statements relevant to their investigation. However, this technique is still not ready for production-level use either in terms of ru ...

Side-channel vulnerabilities can leak sensitive information unconsciously. In this paper, we introduce the usage of Abacus. Abacus is a tool that can analyze secret-dependent control-flow and secret-dependent data-access leakages in binary programs. Unlike ...

Modern software systems heavily use the memory heap. As systems grow more complex and compute with increasing amounts of data, it can be difficult for developers to understand how their programs actually use the bytes that they allocate on the heap and whe ...

The vulnerability of deep neural networks to adversarial attacks has posed significant threats to real-world applications, especially security-critical ones. Given a well-trained model, slight modifications to the input samples can cause drastic changes in ...

Darwin is a genomics co-processor that achieved a 15000x acceleration on long read assembly through innovative hardware and algorithm co-design. Darwins algorithms and hardware implementation were specifically designed for DNA analysis pipelines. This pape ...

This paper presents the implementation of Manticore: a manycore accelerator for parallel RTL simulation. Manticore packs up to 225 custom soft processors running at 475 MHz on a large FPGA. Implementing manycore accelerators on FPGAs is challenging as desi ...

As the usage of FPGAs spreads, engineers will inevitably employ them in ways unforeseen-or unwanted-by their manufacturers. Xilinx's toolchains offer multiple points for customizing the FPGA compilation flow, but all flows must end with Vivado as it is the ...

FPGAs play an increasing role in the reconfigurable accelerator landscape. A key challenge in designing FPGA-based systems is partitioning computation between processor cores and FPGAs. An appropriate division of labor is difficult to predict in advance an ...

Hardware development critically depends on cycle-accurate RTL simulation. However, as chip complexity increases, conventional single-threaded simulation becomes impractical due to stagnant single-core performance. Parendi is an RTL simulator that addresses ...

This paper describes a new technique for parallelizing protein clustering, an important bioinformatics computation for the analysis of protein sequences. Protein clustering identifies groups of proteins that are similar because they share long sequences of ...

In the wake of the pandemic of coronavirus disease 2019 (COVID-19), contact tracing has become a key element of strategies to control the spread of severe acute respiratory syndrome coronavirus-2 (SARS-CoV-2). Given the rapid and intense spread of SARS-CoV ...

Should two private companies have complete control over the world's cellphones? ...

James Richard Larus

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Secured Routines: Language-based Construction of Trusted Execution Environments

Abacus: Precise Side-Channel Analysis

Enclosure: Language-Based Restriction of Untrusted Libraries

Fine-Grain Checkpointing with In-Cache-Line Logging

Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism

WOK: Statistical Program Slicing in Production

Abacus: A Tool for Precise Side-channel Analysis

Detailed Heap Profiling

Watermarking-based Defense against Adversarial Attacks on Deep Neural Networks

IMPACT: Interval-based Multi-pass Proteomic Alignment with Constant Traceback

A 475 MHz Manycore FPGA Accelerator for RTL Simulation

Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats

Auto-Partitioning Heterogeneous Task-Parallel Programs with StreamBlocks

Deploying Decentralized, Privacy-Preserving Proximity Tracing

Parendi: Thousand-Way Parallel RTL Simulation

The ASPLOS 2020 Online Conference Experience: CS Pioneered It, Should We Use It?

Parallel and Scalable Precise Clustering

Early evidence of effectiveness of digital contact tracing for SARS-CoV-2 in Switzerland

Whose Smartphone Is It?

Technical Perspective: The Power of Parallelizing Computations