Publications by James Richard Larus

Related publications (26)

Object-Oriented Recovery for Non-volatile Memory

James Richard Larus, Nachshon Cohen, David Teksen Aksun

New non-volatile memory (NVM) technologies enable direct, durable storage of data in an application's heap. Durable, randomly accessible memory facilitates the construction of applications that do not lose data at system shutdown or power failure. Existing ...

ACM2018

Secured Routines: Language-based Construction of Trusted Execution Environments

James Richard Larus, Edouard Bugnion, Adrien Ghosn

Trusted Execution Environments (TEEs), such as Intel SGX enclaves, use hardware to ensure the confidentiality and integrity of operations on sensitive data. While the technology is available on many processors, the complexity of its programming model and i ...

USENIX ASSOC2019

Abacus: Precise Side-Channel Analysis

James Richard Larus

Side-channel attacks allow adversaries to infer sensitive information from non-functional characteristics. Prior side-channel detection work is able to identify numerous potential vulnerabilities. However, in practice, many such vulnerabilities leak a negl ...

IEEE COMPUTER SOC2021

Enclosure: Language-Based Restriction of Untrusted Libraries

Mathias Josef Payer, James Richard Larus, Edouard Bugnion, Evangelos Marios Kogias, Adrien Ghosn

Programming languages and systems have failed to address the security implications of the increasingly frequent use of public libraries to construct modern software. Most languages provide tools and online repositories to publish, import, and use libraries ...

ACM2021

Fine-Grain Checkpointing with In-Cache-Line Logging

James Richard Larus, Nachshon Cohen, David Teksen Aksun

Non-Volatile Memory offers the possibility of implementing high-performance, durable data structures. However, achieving performance comparable to well-designed data structures in non-persistent (transient) memory is difficult, primarily because of the cos ...

ACM2019

Efficient Logging in Non-Volatile Memory by Exploiting Coherency Protocols

James Richard Larus, Nachshon Cohen

Non-volatile memory (NVM) technologies such as PCM, ReRAM and STT-RAM allow processors to directly write values to persistent storage at speeds that are significantly faster than previous durable media such as hard drives or SSDs. Many applications of NVM ...

ACM2017

Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism

James Richard Larus, Sahand Kashani, Seyedmahyar Emami

The demise of Moore's Law and Dennard Scaling has revived interest in specialized computer architectures and accelerators. Verification and testing of this hardware depend heavily upon cycle-accurate simulation of register-transfer-level (RTL) designs. The ...

Assoc Computing Machinery2023

WOK: Statistical Program Slicing in Production

Bogdan-Alexandru Stoica, James Richard Larus

Dynamic program slicing can significantly reduce the amount of code developers need to inspect by focusing only on program statements relevant to their investigation. However, this technique is still not ready for production-level use either in terms of ru ...

IEEE2019

Abacus: A Tool for Precise Side-channel Analysis

James Richard Larus

Side-channel vulnerabilities can leak sensitive information unconsciously. In this paper, we introduce the usage of Abacus. Abacus is a tool that can analyze secret-dependent control-flow and secret-dependent data-access leakages in binary programs. Unlike ...

IEEE COMPUTER SOC2021

Detailed Heap Profiling

James Richard Larus, Stuart Anthony Byma

Modern software systems heavily use the memory heap. As systems grow more complex and compute with increasing amounts of data, it can be difficult for developers to understand how their programs actually use the bytes that they allocate on the heap and whe ...

ACM2018

Watermarking-based Defense against Adversarial Attacks on Deep Neural Networks

James Richard Larus

The vulnerability of deep neural networks to adversarial attacks has posed significant threats to real-world applications, especially security-critical ones. Given a well-trained model, slight modifications to the input samples can cause drastic changes in ...

IEEE2021

IMPACT: Interval-based Multi-pass Proteomic Alignment with Constant Traceback

James Richard Larus, Sahand Kashani, Stuart Anthony Byma

Darwin is a genomics co-processor that achieved a 15000x acceleration on long read assembly through innovative hardware and algorithm co-design. Darwins algorithms and hardware implementation were specifically designed for DNA analysis pipelines. This pape ...

2019

A 475 MHz Manycore FPGA Accelerator for RTL Simulation

Mohammad Sepehr Pourghannad, James Richard Larus, Sahand Kashani, Seyedmahyar Emami

This paper presents the implementation of Manticore: a manycore accelerator for parallel RTL simulation. Manticore packs up to 225 custom soft processors running at 475 MHz on a large FPGA. Implementing manycore accelerators on FPGAs is challenging as desi ...

Association for Computing Machinery, Inc2024

Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats

James Richard Larus, Sahand Kashani, Seyedmahyar Emami

As the usage of FPGAs spreads, engineers will inevitably employ them in ways unforeseen-or unwanted-by their manufacturers. Xilinx's toolchains offer multiple points for customizing the FPGA compilation flow, but all flows must end with Vivado as it is the ...

IEEE COMPUTER SOC2022

Auto-Partitioning Heterogeneous Task-Parallel Programs with StreamBlocks

James Richard Larus, Seyedmahyar Emami

FPGAs play an increasing role in the reconfigurable accelerator landscape. A key challenge in designing FPGA-based systems is partitioning computation between processor cores and FPGAs. An appropriate division of labor is difficult to predict in advance an ...

ASSOC COMPUTING MACHINERY2022

A Reconfigurable Fabric For Accelerating Large-Scale Datacenter Services

James Richard Larus

To advance datacenter capabilities beyond what commodity server designs can provide, the authors designed and built a composable, reconfigurable fabric to accelerate large-scale software services. They deployed the reconfigurable fabric in a bed of 1,632 s ...

Ieee Computer Soc2015

POSTER: Reducing Transaction Aborts by Looking to the Future

James Richard Larus, Nachshon Cohen

ASSOC COMPUTING MACHINERY2018

Deploying Decentralized, Privacy-Preserving Proximity Tracing

Jean-Pierre Hubaux, Mathias Josef Payer, James Richard Larus, Marcel Salathé, Edouard Bugnion, Carmela González Troncoso, Apostolos Pyrgelis, Wouter Lueks, Sylvain Chatel, Theresa Stadler

2022

Parendi: Thousand-Way Parallel RTL Simulation

James Richard Larus, Thomas Emile Bourgeat, Seyedmahyar Emami

Hardware development critically depends on cycle-accurate RTL simulation. However, as chip complexity increases, conventional single-threaded simulation becomes impractical due to stagnant single-core performance. Parendi is an RTL simulator that addresses ...

ACM2025

The ASPLOS 2020 Online Conference Experience: CS Pioneered It, Should We Use It?

James Richard Larus

2020