Publications by David Novo Bruna

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Carry chains facilitate the implementation of adders and improve the performance of arithmetic circuits in FPGAs. The last version of the commonly used open-source Verilog-to-Routing (VTR) CAD flow now enables modelling carry chains in FPGA architectures. ...

Functional verification occupies a significant amount of the digital circuit design cycle. In this paper, we present a novel approach to improve circuit debugging which not only localizes errors with high confidence, but can also provide semantically-meani ...

Hardware designers and engineers typically need to explore a multi-parametric design space in order to ﬁnd the best conﬁguration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips ...

New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels ...

David Novo Bruna

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Improved carry chain mapping for the VTR flow

FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction

Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case

Non-LUT field-programmable gate arrays

From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis

Automatic support for multi-module parallelism from computational patterns

FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures

A technology mapper for depth-constrained FPGA logic cells