Home

Person

Andreas Peter Burg

About
Privacy
Disclaimer

Graph Chatbot

Related publications (211)

Low-power processor architecture exploration for online biomedical signal analysis

David Atienza Alonso, Luca Benini, Ahmed Yasir Dogan, Andreas Peter Burg, Jeremy Hugues-Felix Constantin

In this study, the authors explore sequential and parallel processing architectures, utilising a custom ultra-low-power (ULP) processing core, to extend the lifetime of health monitoring systems, where slow biosignal events and highly parallel computations ...

Inst Engineering Technology-Iet2012

Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture

Andreas Peter Burg, Jeremy Hugues-Felix Constantin

In this paper, we investigate the benefits of instruction set extensions (ISEs) on a 16-bit microcontroller architecture for software implementations of cryptographic hash functions, using the example of the five SHA-3 final round candidates. We identify t ...

Ieee2012

Standard-Cell Based Memories (SCMs): from Sub-VT to Error-Resilient Systems

Pascal Andreas Meinerzhagen, Andreas Peter Burg

Embedded memories consume an increasingly dominant part of the overall area and power of a large variety of systems-on-chip [ITRS’09]: 1) biomedical implants and wireless sensor networks require robust memories operating in the sub-VT domain; 2) many handh ...

2012

Layered Detection and Decoding in MIMO Wireless Systems

Christoph Studer, Andreas Peter Burg, Nicholas Alexander Preyss

Iterative detection and decoding (IDD) in multiple-input multiple-output (MIMO) wireless systems is known to achieve near channel capacity. The high computational complexity of IDD, however, poses signiﬁcant challenges for practical implementations (in ter ...

IEEE2012

On the Exploitation of the Inherent Error Resilience of Wireless Systems under Unreliable Silicon

Andreas Peter Burg, Georgios Karakonstantis

In this paper, we investigate the impact of circuit misbehavior due to parametric variations and voltage scaling on the performance of wireless communication systems. Our study reveals the inherent error resilience of such systems and argues that sufficien ...

Ieee2012

A 500 fW/bit 14 fJ/bit-access 4kb Standard-Cell Based Sub-VT Memory in 65nm CMOS

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Oskar Andersson

Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-Vt) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforwar ...

2012

Design of Energy Efficient and Dependable Health Monitoring Systems under Unreliable Nanometer Technologies

David Atienza Alonso, Mohamed Mostafa Sabry Aly, Andreas Peter Burg, Georgios Karakonstantis

In this paper we investigate the impact of potential hardware misbehavior induced by reliability issues and scaled voltages in wireless body sensor network (WBSN) nodes. Our study reveals the inherent resilience of popular algorithms in cardiac monitoring ...

ACM Press2012

A 2.78 mm2 65 nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver

Andreas Peter Burg

Iterative detection and decoding (IDD), combined with spatial-multiplexing multiple-input multiple-output (MIMO) transmission, is a key technique to improve spectral efﬁciency in wireless communications. In this paper we present the—to the best of our know ...

2012

VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing

Christoph Studer, Andreas Peter Burg

2012

Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing

David Atienza Alonso, Luca Benini, Ahmed Yasir Dogan, Andreas Peter Burg

This study presents a single-core and a multi-core processor architecture for health monitoring systems where slow biosignal events and highly parallel computations exist. The single-core architecture is composed of a processing core (PC), an instruction m ...

Springer-Verlag Heidelberg2011

Design and failure analysis of logic-compatible multilevel gain-cell-based DRAM for fault-tolerant VLSI systems

Pascal Andreas Meinerzhagen, Andreas Peter Burg

This paper considers the problem of increasing the storage density in fault-tolerant VLSI systems which require only limited data retention times. To this end, the concept of storing many bits per memory cell is applied to area-efficient and fully logic-co ...

ACM Press2011

System-level implications of residual transmit-RF impairments in MIMO systems

Christoph Studer, Andreas Peter Burg

2011

A 772 Mbit/s 8.81 bit/nJ 90 nm CMOS Soft-Input Soft-Output Sphere Decoder

Andreas Peter Burg

IEEE2011

Benchmarking of standard-cell based memories in the sub-VT domain in 65-nm CMOS technology

Pascal Andreas Meinerzhagen, Andreas Peter Burg

In this paper, standard-cell based memories (SCMs) are proposed as an alternative to full-custom sub-VT SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable throughput in the ...

2011

Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders

Yusuf Leblebici, Alessandro Cevrero, Christoph Studer, Andreas Peter Burg

2011

Random Sampling ADC for Sparse Spectrum Sensing

Andreas Peter Burg

Scanning large bandwidths (spectrum sensing) pushes today’s analog hardware to its limits since periodic sampling at Nyquist rate with sufficient resolution is often prohibitively complex. In this paper, we consider a scenario where the signal to be acquir ...

2011

Synthesis strategies for sub-VT systems

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Oskar Andersson

Various synthesis strategies relying on conventional standard-cell libraries (SCLs) are evaluated in order to minimize the energy dissipation per operation in sub-threshold (sub-VT) systems. First, two sub-V T analysis methods are reviewed, both of which a ...

IEEE2011

A 5.35 mm2 10GBASE-T Ethernet LDPC Decoder Chip in 90 nm CMOS

Paolo Ienne, Yusuf Leblebici, Alessandro Cevrero, Andreas Peter Burg

A partially parallel low density parity check (LDPC) decoder compliant with the IEEE 802.3an standard for 10GBASE-T Ethernet is presented. The design is optimized for minimum silicon area and is based on the layered offset-min-sum algorithm which speeds up ...

2010

Systolic-array based regularized QR-decomposition for IEEE 802.11n compliant soft-MMSE detection

Andreas Peter Burg, Carl Christian Sten Dominic Senning

IEEE2010

VLSI Implementation of a Low-Complexity LLL Lattice Reduction Algorithm for MIMO Detection

Christoph Studer, Andreas Peter Burg

Lattice-reduction (LR)-aided successive interference cancellation (SIC) is able to achieve close-to optimum error-rate performance for data detection in multiple-input multiple-output (MIMO) wireless communication systems. In this work, we propose a hardwa ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2010

Page 9 of 11