Publication

A 58mW 1.2 mm 2 HSDPA Turbo Decoder ASIC in 0.13 μm CMOS

Andreas Peter Burg
2008
Conference Papers

Abstract

This paper presents the implementation of the 1.2 mm2 HSDPA turbo decoder ASIC in 0.13 mum CMOS achieves a measured maximum frequency of 246 MHz, which translates to a maximum throughput of 20.2 Mb/s at 5.5 iterations. The peak throughput of 10.8 Mb/s required for HSDPA is achieved at 58 mW and an energy efficiency of 0.7 nJ/b/iter. The number of iterations versus input SNR, as determined by the implemented stopping criterion, and corresponding power measurements.

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A 58mW 1.2 mm 2 HSDPA Turbo Decoder ASIC in 0.13 μm CMOS

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