Publications by Mohammad Najmzadeh

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Multi-gate devices e.g. gate-all-around (GAA) Si nanowires and FinFETs are promising can- didates for aggressive CMOS downscaling. Optimum subthreshold slope, immunity against short channel effect and optimized power consumption are the major benefits of s ...

This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measur ...

In this work we present for the first time correlation of lateral uniaxial tensile strain and I–V characteristics of GAA Si NW n-MOSFET, all measured on the same device. Micro-Raman spectroscopy is employed for direct strain measurement on devices to explo ...

This paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature improved subthreshold swing and Ion/Ioff characteristics. We demonstrate that a lateral strain profile corresponding to at least 0.2 eV band-gap shrinkage at the B ...

In this paper, we report formation of GAA buckled dual Si nanowire MOSFETs including two sub-80 nm Si cores on bulk Si using 0.8 mu m optical lithography and local oxidation for the first time. 0.833 GPa uniaxial tensile stress is measured in the buckled s ...

In this work we report dense arrays of accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-sections in a highly doped regime. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve ⩾2.5 ...

In this paper, we report the first systematic study on electron mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm. 1 x 10(19) cm(-3) n-type channel doping, 5-20 nm Si nanowire wi ...

In this paper, we report for the first time, assessment on mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless (JL) nMOSFETs with cross-section down to 5 nm. This analysis was performed in accumulation regime, as a first ...

In this paper, we report, for the first time, corner effect analysis in the gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found to accumulate and deple ...

In this paper, we investigate the effect of different process parameters on oxidation-induced strain (OIS) into a doubly-clamped silicon nanowire FET to control and finally, enhance carrier mobility. Spacer technology together with sacrificial thermal oxid ...

Mohammad Najmzadeh

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Multi-gate Si nanowire MOSFETs : fabrication, strain engineering and transport analysis

The high-mobility bended n-channel silicon nanowire transistor

Silicon nanowires with lateral uniaxial tensile stress profiles for high electron mobility gate-all-around MOSFETs

Asymmetrically strained all-silicon multi-gate n-Tunnel FETs

Gate-all-around buckled dual Si nanowire nMOSFETs on bulk Si for transport enhancement and digital logic

Accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-section and high uniaxial tensile strain

Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm

Mobility Extraction Assessment in GAA Si NW JL FETs with Cross-Section Down to 5 nm

Local volume depletion/accumulation in GAA Si nanowire junctionless nMOSFETs

Investigation of oxidation-induced strain in a top-down Si nanowire platform