Federico Angiolini

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Related publications (30)

Network-On-Chip Design and Synthesis Outlook

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor Systems-On-Chip (MPSoCs) consisting of complex integrated components communicating with each other at very high-speed rates. Intercommunication ...

2008

NoC Design and Implementation in 65 nm Technology

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent. Networks-on-Chip (NoCs) have been proposed as a scalable solution to both p ...

2007

Bringing NoCs to 65nm

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of Noc-Based interconnect design in nanometer CMOS. The aut ...

2007

Timing-Error-Tolerant Network-on-Chip Design Methodology

Giovanni De Micheli, Federico Angiolini, Luca Benini, Srinivasan Murali

With technology scaling, the wire delay as a fraction of the total delay is increasing, and the communication architecture is becoming a major bottleneck for system performance in systems on chip (SoCs). A communication-centric design paradigm, networks on ...

2007

Improving the Fault Tolerance of Nanometric PLA Designs

Giovanni De Micheli, David Atienza Alonso, Mohamed Haykel Ben Jamaa, Federico Angiolini, Luca Benini

Several alternative building blocks have been proposed to replace planar transistors, among which a prominent spot belongs to nanometric laments such as Silicon NanoWires (SiNWs) and Carbon NanoTubes (CNTs). However, chips leveraging these nanoscale struct ...

2007

Designing Application-Specific Networks on Chips with Floorplan Information

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

With increasing communication demands of processor and memory cores in Systems on Chips (SoCs), scalable Networks on Chips (NoCs) are needed to interconnect the cores. For the use of NoCs to be feasible in today’s industrial designs, a custom-tailored, app ...

2006

Diseño de redes en chip de propósito específico con información de rutado físico

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali, Roman Hermida Correa

The equivalent English title: "Design of Custom Networks-on-Chip with Physical Layout Information" Abstract translated into English: Due to the growing demand of communication between processors and memory devices in Systems-on-Chip (SoCs), recently the ne ...

2006

Reliability Support for On-chip Memories Using Networks-on-Chips

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. ...

2006

Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

On-chip wires are becoming unreliable as the effect of various noise sources increases with technology scaling. This leads to unpredictable timing delay variations on the interconnect wires. There is a significant need to mitigate the effect of parasitics ...

2006

Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

Networks on Chip (NoC) has emerged as the paradigm for designing scalable communication architecture for Systems on Chips (SoCs). Avoiding the conditions that can lead to deadlocks in the network is critical for using NoCs in real designs. Methods that can ...

2006

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