Publications by Federico Angiolini

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Ultrasound imaging is a reference medical diagnostic technique, thanks to its blend of versatility, effectiveness, and moderate cost. The core computation of all ultrasound imaging methods is based on simple formulae, except for those required to calculate ...

The aim of the present invention is to propose a method to provide reliability, power management and load balancing support for multicore systems based on Networks- on-Chip (NoCs) as well as a way to efficiently implement architectural support for this met ...

Volumetric ultrasound (US) is a very promising development of medical US imaging. An under-exploited advantage of volumetric US is the mitigation of the strict probe positioning constrains necessary to acquire 2D scans, potentially allowing the decoupling ...

With increasing communication demands of processor and memory cores in Systems on Chips (SoCs), scalable Networks on Chips (NoCs) are needed to interconnect the cores. For the use of NoCs to be feasible in today’s industrial designs, a custom-tailored, app ...

Networks on Chip (NoC) has emerged as the paradigm for designing scalable communication architecture for Systems on Chips (SoCs). Avoiding the conditions that can lead to deadlocks in the network is critical for using NoCs in real designs. Methods that can ...

With technology scaling, the wire delay as a fraction of the total delay is increasing, and the communication architecture is becoming a major bottleneck for system performance in systems on chip (SoCs). A communication-centric design paradigm, networks on ...

With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor Systems-On-Chip (MPSoCs) consisting of complex integrated components communicating with each other at very high-speed rates. Intercommunication ...

3D ultrasound (US) acquisition acquires volumetric images, thus alleviating a classical US imaging bottleneck that requires a highly-trained sonographer to operate the US probe. However, this opportunity has not been explored in practice, since 3D US machi ...

Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as ...

Through silicon vias (TSVs) provide an efficient way to support vertical communication among different layers of a vertically stacked chip, enabling scalable 3-D networks-on-chip (NoC) architectures. Unfortunately, low TSV yields significantly impact the f ...

The safe and, at the same time, efficient deployment of parallelisable applications on many-core platforms is a challenging task. Theoretical Models of Computation (MoC) require the realistic estimation of task Worst-Case Execution Time (WCET ...

As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. ...

On-chip wires are becoming unreliable as the effect of various noise sources increases with technology scaling. This leads to unpredictable timing delay variations on the interconnect wires. There is a significant need to mitigate the effect of parasitics ...

As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent. Networks-on-Chip (NoCs) have been proposed as a scalable solution to both p ...

3D ultrasound imaging is quickly becoming a refer- ence technique for high-quality, accurate, expressive diagnostic medical imaging. Unfortunately, its computation requirements are huge and, today, demand expensive, power-hungry, bulky processing resources ...

Reconfigurable parallel computing is required to provide high-performance embedded computing, hide hardware complexity, boost software development, and manage multiple workloads when multiple applications are running simultaneously on the emerging network- ...

The equivalent English title: "Design of Custom Networks-on-Chip with Physical Layout Information" Abstract translated into English: Due to the growing demand of communication between processors and memory devices in Systems-on-Chip (SoCs), recently the ne ...

Ultrasound imaging is a technique widely used in medicine to visualize organs and other body structures, capturing their position, size, morphology and any pathological lesions. Its use is unfortunately limited to specialized centers with trained personnel ...

Embedded SoC designs are embracing the many-core paradigm to deliver the required performance to run an ever-increasing number of applications in parallel. Networks-on-Chip (NoC) are considered as a convenient technology to implement many-core embedded pla ...

Real-time (RT) communication support is a critical requirement for many complex embedded applications which are currently targeted to Network-on-chip (NoC) platforms. In this paper, we present novel methods to efficiently calculate worst- case bandwidth an ...

Federico Angiolini

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Efficient Sample Delay Calculation for 2-D and 3-D Ultrasound Imaging

Method to manage the load of peripheral elements within a multicore system

Inexpensive 1024-Channel 3D Telesonography System on FPGA

Designing Application-Specific Networks on Chips with Floorplan Information

Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips

Timing-Error-Tolerant Network-on-Chip Design Methodology

Network-On-Chip Design and Synthesis Outlook

Single-FPGA complete 3D and 2D medical ultrasound imager

Networks on Chips: From Research to Products

Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip

Safe and Efficient Deployment of Data-Parallelisable Applications on Many-Core Platforms: Theory and Practice

Reliability Support for On-chip Memories Using Networks-on-Chips

Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips

NoC Design and Implementation in 65 nm Technology

Tackling the Bottleneck of Delay Tables in 3D Ultrasound Imaging

QoS-Driven Reconfigurable Parallel Computing for NoC-Based Clustered MPSoCs

Diseño de redes en chip de propósito específico con información de rutado físico

Assessment of Image Quality vs. Computation Cost for Different Parameterizations of Ultrasound Imaging Pipelines

An integrated, programming model-driven framework for NoC-QoS support in cluster-based embedded many-cores

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip