Publications by Omer Can Akgun

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Power density and energy dissipation of digital IC's has become one of the main concerns during the recent years. With the increased usage of battery powered devices, ubiquitous computing, and increase in implantable biomedical applications, enhancing ener ...

This manuscript presents the digital hardware realization of a wavelet based event detector for cardiac pacemaker applications. The architecture of the detector is partially folded to minimize hardware cost. An energy model is applied to evaluate the energ ...

This paper presents a flow that is suitable to estimate energy dissipation of digital standard-cell based designs which are determined to operate in the subthreshold regime. The flow is applicable on gate-level netlists, where back-annotated toggle informa ...

Digital circuits operating in the sub-threshold regime are able to perform minimum energy operation at a given delay. In the sub-threshold regime circuit delay, hence the leakage energy consumption depends on the supply voltage exponentially. By reducing t ...

In this paper implementation of a novel completion detection method for self-timed, asynchronous subthreshold circuits is presented. By employing the self-timed operation principle, substantial speed gains in the operation of the asynchronous pipelines can ...

Digital circuits operating in the sub-threshold regime are able to perform minimum energy operation at a given delay. In the sub-threshold regime the circuit delay, and hence, the leakage energy consumption depend on the supply voltage exponentially. By re ...

In this paper the advantages of using Differential Cascode Voltage Switch Pass Gate (DCVSPG) logic with regard to standard CMOS for subthreshold operation are presented. The two families are compared in terms of their performance and Energy-Delay-Product ( ...

In this paper a novel completion detection method for self-timed, asynchronous subthreshold circuits is presented. By employing the self-timed operation principle, substantial speed gains in the operation of the asynchronous pipelines can be realized. The ...

This paper describes the implementation of a 12-bit 230 MS/s pipelined ADC using a conventional 1.8V, 0.18μm digital CMOS process. Two-stage folded cascode OTA topology is used for improved settling performance. Extreme low-skew (less than 3ps peak-to-peak ...

Omer Can Akgun

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Energy efficiency enhancement of sub-threshold digital CMOS : modeling, technology selection and architectural exploration

Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-Vt Domain By Architectural Folding

High-Level Energy Estimation in the Sub-VT Domain: Simulation and Measurement of a Cardiac Event Detector

Energy Efficiency Comparison of Asynchronous and Synchronous Circuits Operating in the Sub-Threshold Regime

Design of Completion Detection Circuits for Self-timed Systems Operating in Subthreshold Regime

A Current Sensing Completion Detection Method for Asynchronous Pipelines Operating In the Sub-threshold Regime

Weak Inversion Performance of CMOS and DCVSPG Logic Families in Sub-300mV Range

Current Sensing Completion Detection for Subthreshold Asynchronous Circuits

A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18um CMOS technology