Publications by Giovanni De Micheli

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Individual transistors based on emerging reconfigurable nanotechnologies exhibit electrical conduction for both types of charge carriers. These transistors (referred to as Reconfigurable Field-Effect Transistors (RFETs)) enable dynamic reconfiguration to d ...

Real-time and multi-target detection by wireless implantable devices is of increasing interest for chronic patients. In this work, electrode sharing is proposed to minimize the size of the implantable device when several three-electrode-based sensing sites ...

Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient network on chip (NoC) interconnect for a 3-D SoC that meets not only the applicat ...

Background: Structural genomics initiatives are producing increasing numbers of three-dimensional (3D) structures for which there is little functional information. Structure-based annotation of molecular function is therefore becoming critical. We previous ...

Routing multiplexers based on pass-transistors or transmission gates are an essential components in many digital integrated circuits. However, whatever structure is employed, CMOS multiplexers have two major limitations: 1) their delay is linearly related ...

The sensitive analysis of proteins is central to disease diagnosis. The detection and investigation of angiogenic and inflammatory ligands in the tumor tissue can further improve the level of knowledge of the cancer disease by capturing the heterogeneity a ...

The advent of 3-D fabrication technology makes it possible to stack a large amount of last-level cache memory onto a multi-core die to reduce off-chip memory accesses and, thus, increases system performance. However, the higher power density (i.e., power d ...

We present a synthesis framework to map logic networks into quantum circuits for quantum computing. The synthesis framework is based on lookup-table (urn networks, which play a key role in conventional logic synthesis. Establishing a connection between LUT ...

Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges to maintain manufacturing yield rates and reliable devices in their expecte ...

Asthe currentMOSFET scaling trend is facing strong limitations, technologies exploiting novel degrees of freedom at physical and architecture level are promising candidates to enable the continuation of Moore's predictions. In this paper, we report on the ...

In three-dimensional (3D) integrated circuits, the effect of process variations on clock skew differs from 2D circuits. The combined effect of inter-die and intra-die process variations on the design of 3D clock distribution networks is considered in this ...

New tendencies envisage Multi-Processor Systems-On-Chip (MPSoCs) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute multiple applications (games, video), while meeting additional design constrain ...

This paper reports the characterization of an electrochemical biosensor for the continuous monitoring of Naproxen based on cytochrome P450. The electrochemical biosensor is based on the drop-casting of multi-walled carbon-nanotubes (MWCNTs) and microsomal ...

In recent years, Boolean methods in logic synthesis have been drawing the attention of EDA researchers due to the continuous push to advance quality of results. Boolean methods require high computational cost, as they rely on complete functional properties ...

Traditional logic synthesis faces challenges of meeting the requirements demanded by the many emerging nanotech-nologies that are based on logic models different from standard CMOS. Several emerging nanodevices including Quantum-dot Cellular Automata (QCA) ...

To tackle the increasing communication complexity of multi-core systems, scalable Networks on Chips (NoCs) are needed to interconnect the processor, memory and hardware cores of the systems. For the use of NoCs to be feasible in today's industrial designs, ...

The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) decoder is a critical part since it bridges the sublithographic wires to the outer circuit ...

This paper presents a switched-capacitor (SC) current integrator circuit for impedance measurement of tethered bilayer lipid membrane (tBLM) biosensors. The circuit comprises a small number of high performance components enabling enhanced experimental flex ...

As the communication requirements of current and future Multiprocessor Systems on Chips (MPSoCs) continue to increase, scalable communication architectures are needed to support the heavy communication demands of the system. This is reflected in the recent ...

In this paper we present the top-down fabrication of gate-all-around (GAA) and body-tied @W-gate devices by a combination of etching and oxidation steps resulting in a local silicon-on-insulator structure. The GAA has advantages in terms of enhanced curren ...

Giovanni De Micheli

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Utilizing XMG-based Synthesis to Preserve Self-Duality for RFET-Based Circuits

A Current-Mode Potentiostat for Multi-Target Detection Tested with Different Lactate Biosensors

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chips

Clustering protein environments for function prediction: finding PROSITE motifs in 3D

Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure

SiNW-FET in-Air Biosensors for High Sensitive and Specific Detection in Breast Tumor Extract

Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache

LUT-Based Hierarchical Reversible Logic Synthesis

Reliability-Aware Design for Nanometer-Scale Devices

Top-Down Fabrication of Gate-All-Around Vertically-Stacked Silicon Nanowire FETs with Controllable Polarity

Effects of Process Variations on 3-D Global Clock Distribution Networks

HW-SW Emulation Framework for Temperature-Aware Design in MPSoCs

Continuous monitoring of Naproxen by a cytochrome P450-based electrochemical sensor

Extending Boolean Methods for Scalable Logic Synthesis

Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies

Method to design network-on-chip (noc)-based communication systems

Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories

Real-time high-sensitivity impedance measurement interface for tethered BLM biosensor arrays

An Application-Specific Design Methodology for STbus Crossbar Generation

Prospects for logic-on-a-wire