Publication

Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies

Giovanni De Micheli, Mathias Soeken, Eleonora Testa, Odysseas Zografos
2017
Conference Papers

Abstract

Traditional logic synthesis faces challenges of meeting the requirements demanded by the many emerging nanotech-nologies that are based on logic models different from standard CMOS. Several emerging nanodevices including Quantum-dot Cellular Automata (QCA) and Spin Torque Majority Gates (STMG) are based on majority logic. In addition, technology constraints require to restrict the number of fan-outs or impose difficulties in realizing inversions. In this paper, we use a majority-based logic synthesis approach to synthesize inversion-free networks with restricted fan-out. We propose one algorithm that propagates all inversions to the primary inputs and another algorithm that limits the number of fan-outs of each majority gate. These algorithms show significant impact on QCA- and STMG-based circuits. Experimental results demonstrate that the average area-delay-energy product can be improved by 3.1× in QCA-based circuits and from 2.9× to 8.1× for STMG-based circuits.

Official source

https://infoscience.epfl.ch/entities/publication/93349ae9-c996-4780-891c-479b31a2fc10

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Giovanni De Micheli, Mathias Soeken, Eleonora Testa, Odysseas Zografos
2017
Conference Papers

Abstract

Official source

https://infoscience.epfl.ch/entities/publication/93349ae9-c996-4780-891c-479b31a2fc10

About this result

Related concepts (32)

Logic optimization

Logic optimization is a process of finding an equivalent representation of the specified logic circuit under one or more specified constraints. This process is a part of a logic synthesis applied in digital electronics and integrated circuit design. Generally, the circuit is constrained to a minimum chip area meeting a predefined response delay. The goal of logic optimization of a given circuit is to obtain the smallest logic circuit that evaluates to the same values as the original one.

Dependence logic

Dependence logic is a logical formalism, created by Jouko Väänänen, which adds dependence atoms to the language of first-order logic. A dependence atom is an expression of the form , where are terms, and corresponds to the statement that the value of is functionally dependent on the values of . Dependence logic is a logic of imperfect information, like branching quantifier logic or independence-friendly logic (IF logic): in other words, its game-theoretic semantics can be obtained from that of first-order logic by restricting the availability of information to the players, thus allowing for non-linearly ordered patterns of dependence and independence between variables.

In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals. Register-transfer-level abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived.

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