Publications by Giovanni De Micheli

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Memristive biosensors have been proved as excellent candidates for ultrasensitive biosensing. In this work, a novel portable bio-detection system based on memristive biosensors is designed, developed and tested for providing a significantly fast, automatic ...

For diagnostic and therapeutic purposes an accurate determination of multiple metabolites is often required. Amperometric devices are attractive tools to quantify biological compounds due to the direct conversion of a biochemical event to a current. This r ...

Two diverse manufacturing techniques for building 3-D integrated systems are vertical integration with Through-Silicon-Vias (TSVs), also referred to as 3-D TSV integration, and 3-D monolithic integration. In this paper, we present a hybrid integration sche ...

3D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. In 3DMI technology the 3D contacts, connecting different active layers, are in the order of few 100 nm. Given the advantage of ...

A Majority-Inverter Graph (MIG) is a recently introduced logic representation form whose algebraic and Boolean properties allow for efficient logic optimization. In particular, when considering logic depth reduction, MIG algorithms obtained signific ...

Many emerging nanotechnologies realize majority gates as primitive building blocks and they benefit from a majority-based synthesis. Recently, Majority-Inverter Graphs (MIGs) have been introduced to abstract these new technologies. We present optimi ...

The majority-inverter graph (MIG) is a homogeneous logic network widely used in logic synthesis for majority-based emerging technologies. Many logic optimization algorithms have been proposed for MIGs, including rewriting, resubstitution, and graph mapping ...

Hierarchical reversible logic synthesis can find quantum circuits for large combinational functions. The price for a better scalability compared to functional synthesis approaches is the requirement for many additional qubits to store temporary results of ...

Many Networks-on-Chip (NoC) applications exhibit one or more critical traffic flows that require hard Quality of Service (QoS). Guaranteeing bandwidth and latency for such real time flows is crucial. In this paper, we present novel methods to efficiently c ...

This paper first explores the effects of faults on circuits implemented with controllable-polarity transistors. We propose a new fault model that suits the characteristics of these devices, and report the results of a SPICE-based analysis of the effects of ...

As demands for computing have been continuously increasing, various solutions have been proposed. Some approaches deal with improving algorithms and software programs, mainly through the tuning of advanced heuristics and learning methods. Some other tackle ...

Logic synthesis is an ensemble of algorithms that optimizes digital circuit representations and maps them to a chosen technology. Minimizing the number of gates is essential to reduce area occupation and power consumption. As the problem is intractable, he ...

A new approach for inserting repeaters in 3-D interconnects is proposed. The allocation of repeaters along an interplane interconnect is iteratively determined. The proposed approach is compared with two other techniques based on conventional methods used ...

Rapid single-flux quantum (RSFQ) is one of the most advanced superconductive electronics technologies. SFQ systems operate at tens of gigahertz with up to three orders of magnitude smaller power as compared to CMOS. In conventional SFQ systems, most gates ...

This paper proposes a versatile mapping approach that has three objectives: i) it can map from one technology-independent graph representation to another; ii) it can map to a cell library; iii) it supports logic rewriting. The method is cut-based, mitigate ...

In this paper, we demonstrate a steep Subthreshold Slope (SS) silicon FinFET with Schottky-barrier source/drain. The device shows a minimal SS of 3.4 mV/dec and an average SS of 6.0 mV/dec over 5 decades of current swing. Ultra-low leakage floor of 0.06 pA ...

Adiabatic quantum-flux parametron (AQFP) is an energy-efficient superconducting technology. Buffer and splitter (B/S) cells must be inserted to an AQFP circuit to meet the technology-imposed constraints on path balancing and fanout branching. These cells a ...

Giovanni De Micheli

Chat with Graph Search

Portable Memristive Biosensing System as Effective Point-of-Care Device for Cancer Diagnostics

Multiwalled Carbon Nanotubes for Amperometric Array-Based Biosensors

3.5-D Integration: A Case Study

Cell Transformations and Physical Design Techniques for 3D Monolithic Integrated Circuits

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chip

Optimizing Majority-Inverter Graphs with Functional Hashing

Inversion optimization in majority-inverter graphs

Late Breaking Results: Majority-inverter Graph Minimization by Design Space Exploration

Reversible Pebble Games For Reducing Qubits In Hierarchical Quantum Circuit Synthesis

A Method for Calculating Hard QoS Guarantees for Networks-on-Chip

On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

Roundtable Panel Discussion at DAC 2019: Evolutionary Computing or Heuristic Forever?

An Enhanced Resubstitution Algorithm for Area-Oriented Logic Optimization

Logic Synthesis for Emerging Technologies

The Combinational-Complexity Game For Symmetric Functions

Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits

Towards Multiphase Clocking in Single-Flux Quantum Systems

A Versatile Mapping Approach for Technology Mapping and Graph Optimization

A Schottky-Barrier Silicon FinFET with 6.0 mV/dec Subthreshold Slope over 5 Decades of Current

Beyond Local Optimality of Buffer and Splitter Insertion for AQFP Circuits