Lecture

Parallel Port & Nios II Interrupts

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CS-476: Embedded system design

Hardware-software co-design is a well known concept in embedded system design.It is also a concept required in designing FPGA-accelerators in data-centers.This course teaches how to transform algorithms in smart hardware-software solutions. ...

Description

This lecture covers the design of a programmable parallel port interface for an Avalon bus, including the methodology, VHDL realization, and testing. It also explains the features and specifications of the typical SOPC system with Nios II CPU, focusing on parallel input/output interfaces. The lecture delves into the architecture of the Nios II processor, its core features, programming model, and interrupt services. It details the registers, control logic, and memory architecture of the Nios II core, emphasizing the trade-offs in system implementation. Additionally, it discusses the programming model registers, interrupt handling, and the relationship between ienable, ipending, and PIE for interrupt generation.

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Instructor

Ties Jan Henderikus Kluter

Since January 2011: Teaching digital systems at the Swiss Federal Institute of Technology, Lausanne Switzerland Since August 2009: Teaching responsible for digital systems at the university of applied science of Bern, Bienne Switzerland 2003-2010: Ph.D. candidate at the Swiss Federal Institute of Technology, Lausanne Switzerland 2002-2003: Product development team leader in the infotainment group of Agere Systems, Nieuwegein The Netherlands. 1997-2003: Design Engineer in the design services group of Dedris Embedded Algorithms/Frontier Design BV./Adelante Technologies, Tiel The Netherlands 1996-1997: Assistant R&D at the faculty of computer controlled systems and computer techniques University of Twente, Enschede The Netherlands 1992-1996: MSc. education at the Technical University of Twente, Enschede The Netherlands 1988-1992: Bc. edudation at the Higher Technical School of Groningen, Groningen The Netherlands

Official source

Ontological neighbourhood

Computer engineering

Hardware engineering: Microprocessors

High-performance computing: Real-time computing

Related concepts (32)

Interrupt

In digital computers, an interrupt (sometimes referred to as a trap) is a request for the processor to interrupt currently executing code (when permitted), so that the event can be processed in a timely manner. If the request is accepted, the processor will suspend its current activities, save its state, and execute a function called an interrupt handler (or an interrupt service routine, ISR) to deal with the event.

Interrupt handler

In computer systems programming, an interrupt handler, also known as an interrupt service routine or ISR, is a special block of code associated with a specific interrupt condition. Interrupt handlers are initiated by hardware interrupts, software interrupt instructions, or software exceptions, and are used for implementing device drivers or transitions between protected modes of operation, such as system calls. The traditional form of interrupt handler is the hardware interrupt handler.

Non-maskable interrupt

In computing, a non-maskable interrupt (NMI) is a hardware interrupt that standard interrupt-masking techniques in the system cannot ignore. It typically occurs to signal attention for non-recoverable hardware errors. Some NMIs may be masked, but only by using proprietary methods specific to the particular NMI. An NMI is often used when response time is critical or when an interrupt should never be disabled during normal system operation.

Interrupt request

In a computer, an interrupt request (or IRQ) is a hardware signal sent to the processor that temporarily stops a running program and allows a special program, an interrupt handler, to run instead. Hardware interrupts are used to handle events such as receiving data from a modem or network card, key presses, or mouse movements. Interrupt lines are often identified by an index with the format of IRQ followed by a number. For example, on the Intel 8259 family of programmable interrupt controllers (PICs) there are eight interrupt inputs commonly referred to as IRQ0 through IRQ7.

Programmable interrupt controller

In computing, a programmable interrupt controller (PIC) is an integrated circuit that helps a microprocessor (or CPU) handle interrupt requests (IRQ) coming from multiple different sources (like external I/O devices) which may occur simultaneously. It helps prioritize IRQs so that the CPU switches execution to the most appropriate interrupt handler (ISR) after the PIC assesses the IRQ's relative priorities. Common modes of interrupt priority include hard priorities, rotating priorities, and cascading priorities.

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