Lectures related to Register-transfer level

Robust Systems: Emerging Technologies and User Experience

Explores Professor Subashish Mitra's research on robust systems and pressing issues in ICT, emphasizing the importance of understanding the entire system for innovative solutions.

Lithography: General Concepts and Mask Fabrication MOOC: Micro and Nanofabrication (MEMS)

Covers lithography concepts, mask fabrication, UV lithography, and emerging techniques.

Energy-Efficient Data Centers

Explores the YINZ project's innovative solutions to reduce energy consumption in data centers through interdisciplinary collaborations and cutting-edge technologies.

Static Timing Analysis Log in to Mediaspace to watch this video

Explores static timing analysis in digital system design, covering setup and hold time requirements, critical paths, and timing conditions.

Semicustom RTL Design: Frontend with Synthesis Log in to Mediaspace to watch this video

Covers the fundamentals of VLSI design, focusing on the semi-custom design flow.

Formally Verified Chisel Designs Log in to Mediaspace to watch this video

Explores formally verifying Chisel designs using SMT solvers and covers examples like delayed assertions and proofs by induction.

Synchronous Digital Circuits: Principles and Design Log in to Mediaspace to watch this video

Covers principles of synchronous RTL design, custom digital circuits, Y-Diagram visualization, signal classes, and hierarchy management.

Basic Synchronous Digital Circuits and RTL Design Log in to Mediaspace to watch this video

Covers pulse generation, edge detection, common design mistakes, and clock/reset signals in logic circuits.

Semicustom RTL Design: Backend Log in to Mediaspace to watch this video

Explores the backend design flow in semicustom ASIC design, covering layout, clock tree generation, and tapeout preparation.

Semicustom RTL Design: Design Flow and Standard Cells Log in to Mediaspace to watch this video

Explores the RTL design flow, chip-level integration, standard cells, and static timing analysis in VLSI design.

Design and Fundamentals of Digital Systems Log in to Mediaspace to watch this video

Explores the construction and key concepts of Digital Systems, including binary representation, hardware-software differences, and implementation options.

Hardware Verification using High-Level Design Languages Log in to Mediaspace to watch this video

Explores challenges in hardware verification, clear specifications, speculation harm, and cycle-precise semantics.

Project: Video Game Log in to Mediaspace to watch this video

Covers the organization, objectives, project ideas, graphics enhancement, advanced adapters, and alternative interfaces for a video game project.

VHDL for Synthesis Log in to Mediaspace to watch this video

Covers basic VHDL constructs for RTL design, including arithmetic, multiplexers, registers, and instantiation.

VGA Adapter Log in to Mediaspace to watch this video

Covers the design of a VGA Adapter for a Pong game project and explains the VGA interface architecture and video signal generation options.

Physical Design Basics Log in to Mediaspace to watch this video

Introduces the basics of physical design in VLSI chip design, emphasizing layout features, power supply wiring, and gate layout optimization.

SecChisel: Security Verification of Secure Processor Architectures Log in to Mediaspace to watch this video

Presents the SecChisel framework for verifying security properties of secure processor architectures at design-time.

Hardware Description Languages Log in to Mediaspace to watch this video

Explores the history and significance of Hardware Description Languages in automating design processes and describing parallel hardware.

Simulation-Based Verification Log in to Mediaspace to watch this video

Explores simulation-based verification in VLSI systems using compiled-code and event-driven algorithms.

In-System Debug and Custom AXI IP Log in to Mediaspace to watch this video

Covers in-system debug, marking nets, generating debug IP, and reading from a custom AXI IP.