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Concept

Clock recovery

Related publications (17)

Cross-chain payment protocols with success guarantees

Vincent Gramoli

In this paper, we consider the problem of cross-chain payment whereby customers of different escrows-implemented by a bank or a blockchain smart contract-successfully transfer digital assets without trusting each other. Prior to this work, cross-chain paym ...

SPRINGER2023

Kramers Kronig detection of four 20 Gbaud 16-QAM channels using Kerr combs for a shared phase estimation

Tobias Kippenberg, Maxim Karpov, Martin Hubert Peter Pfeiffer, Arne Kordts, Fatemeh Alishahi

We experimentally demonstrate Kramers-Kronig detection of four 20 Gbaud 16-quadrature-amplitude-modulated (QAM) channels after 50 km fiber transmission using two soliton Kerr combs as signal sources and local oscillators. The estimated carrier phase at the ...

OPTICAL SOC AMER2020

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

Andrea Bonetti

As an increase of intelligent and self-powered devices is forecasted for our future everyday life, the implementation of energy-autonomous devices that can wirelessly communicate data from sensors is crucial. Even though techniques such as voltage scaling ...

EPFL2019

4x40 Gb/s 2 pJ/bit Optical RX with 8ns Power-on and CDR-Lock Time in 14nm CMOS

Alessandro Cevrero, Thomas Toifl, Ilter Ozkaya

We report a low-power 4-channel NRZ optical RX including a digital burst-mode CDR measured up to 40Gb/s/lane in 14nm CMOS. The RX, designed for 850nm VCSEL based optical links, can wake-up and achieve phase-lock in 8ns at BER

IEEE2018

Adaptive Receiver Design for High Speed Optical Communication

Ilter Ozkaya

Conventional input/output (IO) links consume power, independent of changes in the bandwidth demand by the system they are deployed in. As the system is designed to satisfy the peak bandwidth demand, most of the time the IO links are idle but still consumin ...

EPFL2018

A 60 Gb/s 1.9 pJ/bit NRZ Optical-Receiver with Low Latency Digital CDR in 14nm CMOS FinFET

Yusuf Leblebici, Alessandro Cevrero, Thomas Toifl, Lukas Kull, Ilter Ozkaya

This work reports a low power implementation of a 60Gb/s NRZ optical receiver (RX) in 14nm bulk CMOS finFET featuring a first-order digital CDR with high jitter tolerance (JTOL). The design includes a single phase-rotator (PR) with low complexity control l ...

2017

Converse effect of pressure on the quadrupolar and magnetic transition in Ce3Pd20Si6

Henrik Moodysson Rønnow, Julio Antonio Larrea Jiménez

The heavy fermion compound Ce3Pd20Si6 displays unconventional quantum criticality as the lower of two consecutive phase transitions is fully suppressed by magnetic field. Here we report on the effects of pressure as an additional tuning parameter. Specific ...

Amer Physical Soc2016

Applicability Of New Approaches Of Sensor Orientation To Micro Aerial Vehicles

Jan Skaloud, Martin Rehak

This study highlights the benefits of precise aerial position and attitude control in the context of mapping with Micro Aerial Vehicles (MAVs). Accurate mapping with MAVs is gaining importance in applications such as corridor mapping, road and pipeline ins ...

Copernicus Gesellschaft Mbh2016

Efficient Testing of Recovery Code Using Fault Injection

George Candea

A critical part of developing a reliable software system is testing its recovery code. This code is traditionally difficult to test in the lab, and, in the field, it rarely gets to run; yet, when it does run, it must execute flawlessly in order to recover ...

2011

An Extensible Technique for High-Precision Testing of Recovery Code

George Candea, Radu Banabic

Thorough testing of software systems requires ways to productively employ fault injection. We describe a technique for automatically identifying the errors exposed by shared libraries, finding good injection targets in program binaries, and producing corre ...

2010

Clock-Offset Tracking Software Algorithms For IR-UWB Energy-Detection Receivers

Jean-Yves Le Boudec, Ruben Merz

We present a clock-offset tracking algorithm for impulse-radio ultra-wide band (IR-UWB) energy-detection receivers. There is a complexity versus performance trade-off for the design of IR-UWB energy-detection receivers: Extremely low-complexity energy-dete ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

A Power-Efficient Clock and Data Recovery Circuit in 0.18-um CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

Yusuf Leblebici, Seyed Armin Tajalli, Paul Victor Georges Muller

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two ma ...

2007

Tradeoffs in Design of Low-Power Gated-Oscillator CDR Circuits

Yusuf Leblebici, Seyed Armin Tajalli, Paul Victor Georges Muller

This article describes some techniques for implementing low- power clock and data recovery (CDR) circuits based on gated- oscillator (GO) topology for short distance applications. Here, the main tradeoffs in design of a high performance and power-efficient ...

2007

A standard CMOS multi-channel single-chip receiver for multi-gigabit optical data communications

Paul Victor Georges Muller

As dictated by ongoing technology scaling and the advent of multi-core systems, each new generation of microprocessors and digital signal processors provides higher computing power and data throughput. However, the available bandwidth of the input/output ( ...

EPFL2006

Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini

On-chip wires are becoming unreliable as the effect of various noise sources increases with technology scaling. This leads to unpredictable timing delay variations on the interconnect wires. There is a significant need to mitigate the effect of parasitics ...

2006

A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18µm digital CMOS technology

Yusuf Leblebici, Seyed Armin Tajalli, Paul Victor Georges Muller

This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying ...

2005

Jitter Tolerance Analysis of Clock and Data Recovery Circuits using Matlab and VHDL-AMS

Yusuf Leblebici, Paul Victor Georges Muller

In the scope of the development of a complete top-down design flow targeting clock and data recovery circuits for high-speed data links, we present two methods to analyze the jitter tolerance of such links, based on statistical simulation of incoming data ...

2005