Publication

A Wideband MDLL with Jitter Reduction Scheme for Forwarded Clock Serial Links in 40 nm CMOS

Yusuf Leblebici
2016
Conference Papers

Abstract

This paper presents the design and implementation of a multiplying delay-locked loop (MDLL) in 40 nm bulk CMOS process, which can be used as clock and data recovery (CDR) unit in source-synchronous wire-line communications. The MDLL multiplies the reference frequency and delivers differential inphase (I) and quadrature (Q) clocks by generating 8 equally spaced clock phases and combining these phases appropriately. A technique for reducing deterministic jitter (DJ) in MDLL is proposed. The prototype dissipates 1.1-1.8 mW over output frequency range of 2.6-6.4 GHz, while the RMS jitter and I/Q mismatch remain below 3ps rms and 5 degree, respectively, over the entire range. The core size occupies 60x40 um2 silicon area.

Official source

https://infoscience.epfl.ch/entities/publication/e274c02a-722c-4af0-ace8-27012ecceb10

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Yusuf Leblebici
2016
Conference Papers

Abstract

Official source

https://infoscience.epfl.ch/entities/publication/e274c02a-722c-4af0-ace8-27012ecceb10

About this result

Related concepts (32)

Frequency synthesizer

A frequency synthesizer is an electronic circuit that generates a range of frequencies from a single reference frequency. Frequency synthesizers are used in many modern devices such as radio receivers, televisions, mobile telephones, radiotelephones, walkie-talkies, CB radios, cable television converter boxes, satellite receivers, and GPS systems. A frequency synthesizer may use the techniques of frequency multiplication, frequency division, direct digital synthesis, frequency mixing, and phase-locked loops to generate its frequencies.

Frequency divider

A frequency divider, also called a clock divider or scaler or prescaler, is a circuit that takes an input signal of a frequency, , and generates an output signal of a frequency: where is an integer. Phase-locked loop frequency synthesizers make use of frequency dividers to generate a frequency that is a multiple of a reference frequency. Frequency dividers can be implemented for both analog and digital applications. Analog frequency dividers are less common and used only at very high frequencies.

Phase-locked loop

A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. There are several different types; the simplest is an electronic circuit consisting of a variable frequency oscillator and a phase detector in a feedback loop. The oscillator's frequency and phase are controlled proportionally by an applied voltage, hence the term voltage-controlled oscillator (VCO).

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A Wideband MDLL with Jitter Reduction Scheme for Forwarded Clock Serial Links in 40 nm CMOS

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