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Concept

Real-time clock

Related publications (12)

Virtual Capacitor Concept for Computationally Efficient and Flexible Real-Time MMC Model

Drazen Dujic, Stefan Milovanovic, Min Luo

This paper demonstrates the splitting of the modular multilevel converter real-time simulation model into several independent parts through the use of the virtual capacitor concept. As a result, the number of state-space matrices the real-time solver needs ...

2021

Virtual Capacitor Concept for Effective Real-Time MMC Simulations

Drazen Dujic, Stefan Milovanovic, Min Luo

In this paper, the real-time simulation model of the modular multilevel converter was split into several independent parts through the use of the virtual capacitor concept. As a result, the number of state-space matrices the real-time solver needs to take ...

2021

Rocker oscillator time bases

Simon Nessim Henein, Ilan Vardi

Since the invention of the pendulum clock by Christiaan Huygens in 1657, precision timekeepers have been regulated by oscillators. Although the pendulum is not an isochronous oscillator, its introduction as a time basis for clock regulation led to a signif ...

2021

Low-power clock distribution networks for 3-D ICs

Giovanni De Micheli, Vasileios Pavlidis, Somayyeh Rahimian Omam

Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low-power alternatives to conventional cl ...

2012

A Low-Overhead Method for Pre-bond Test of Resonant 3-D Clock Distribution Networks

Giovanni De Micheli, Vasileios Pavlidis, Somayyeh Rahimian Omam

2012

The Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu, Wayne Burleson

In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock s ...

Ieee2012

Dispensing and Hermetic Sealing Rb in a Miniature Reference Cell for Integrated Atomic Clocks

Herbert Shea, Thomas Maeder, Peter Ryser, Vinu Lalgudi Venkatraman, Fabrizio Vecchio

An innovative method for filling and sealing the reference cell for a Rubidium (Rb) integrated atomic clock is presented. We used a simple, low-temperature solder sealing technique for producing mini-cells of the size of 12 x 10 x 2 mm, suitable for Rb min ...

Elsevier2011

Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits

Giovanni De Micheli, Vasileios Pavlidis, Somayyeh Rahimian Omam

Springer-Verlag2011

YaQ: An Architecture for Real-Time Navigation and Rendering of Varied Crowds

Daniel Thalmann, Jonathan Maim, Barbara Yersin

The YaQ software platform is a complete system dedicated to real-time crowd simulation and rendering. Fitting multiple application domains, such as video games and VR, YaQ aims to provide efficient algorithms to generate crowds comprising up to thousands o ...

Institute of Electrical and Electronics Engineers2009

A Power-Efficient Clock and Data Recovery Circuit in 0.18-um CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

Yusuf Leblebici, Seyed Armin Tajalli, Paul Victor Georges Muller

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two ma ...

2007

Building Blocks for an Ultra Low-Power MEMS-based Radio

Christian Enz

The recent advances made in MEMS and particularly in RF MEMS technology are enabling new architectures for the integration of RF transceivers with improved performance and smaller size. Several fundamental building blocks benefit from the availability of h ...

2007

A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18µm digital CMOS technology

Yusuf Leblebici, Seyed Armin Tajalli, Paul Victor Georges Muller

This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying ...

2005