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Concept

Functional completeness

Related publications (20)

Scalable Logic Rewriting Using Don’t Cares

Giovanni De Micheli, Alessandro Tempia Calvino

Logic rewriting is a powerful optimization technique that replaces small sections of a Boolean network with better implementations. Typically, exact synthesis is used to compute optimum replacement on-the-fly, with possible support for Boolean don't cares. ...

2024

Brain microstructural and functional MRI: developments and application to a rat model of Alzheimer's disease

Yujian Diao

Magnetic resonance imaging (MRI) has been a valuable tool in investigating the pathological cascade of Alzheimer's disease (AD) and its progression, which are still open questions. Although some MRI-derived hallmarks in terms of functional connectivity and ...

EPFL2023

Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies

Giovanni De Micheli, Heinz Riener, Akash Kumar

Emerging reconfigurable nanotechnologies allow the implementation of self-dual functions with a fewer number of transistors as compared to traditional CMOS technologies. To achieve better area results for Reconfigurable Field-Effect Transistors (RFET)-base ...

IEEE2021

Time-resolved effective connectivity in task fMRI: Psychophysiological interactions of Co-Activation patterns

Dimitri Nestor Alice Van De Ville, Thomas William Arthur Bolton, Lorena Gonçalves de Alcântara e Freitas Krikler

Investigating context-dependent modulations of Functional Connectivity (FC) with functional magnetic resonance imaging is crucial to reveal the neurological underpinnings of cognitive processing. Most current analysis methods hypothesise sustained FC withi ...

ACADEMIC PRESS INC ELSEVIER SCIENCE2020

Structural Rewriting in XOR-Majority Graphs

Giovanni De Micheli, Mathias Soeken

In this paper, we present a structural rewriting method for a recently proposed XOR-Majority graph (XMG), which has exclusive-OR (XOR), majority-of-three (MAJ), and inverters as primitives. XMGs are an extension of Majority-Inverter Graphs (MIGs). Previous ...

ASSOC COMPUTING MACHINERY2019

On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis

Giovanni De Micheli, Mathias Soeken, Heinz Riener, Winston Jason Haaswijk

The paper presents a generalization of DAG-aware AIG rewriting for k-feasible Boolean networks, whose nodes are k-input lookup tables (k-LUTs). We introduce a high-effort DAG-aware rewriting algorithm, called cut rewriting, which uses exact synthesis to co ...

IEEE2019

The Complexity of Self-Dual Monotone 7-Input Functions

Giovanni De Micheli, Mathias Soeken, Eleonora Testa, Winston Jason Haaswijk

The study of the complexity of Boolean functions has recently found applications in logic synthesis and optimization algorithms, as for instance in logic rewriting. Previous works have focused on the minimum length of Boolean chains for functions up to 5 i ...

2019

Improvements to Boolean resynthesis

Giovanni De Micheli, Mathias Soeken, Luca Gaetano Amarù

In electronic design automation Boolean resynthesis techniques are increasingly used to improve the quality of results where algebraic methods hit local minima Boolean methods rely on complete functional properties of a logic circuit, preferably including ...

IEEE2018

Classifying Functions with Exact Synthesis

Giovanni De Micheli, Mathias Soeken, Eleonora Testa, Winston Jason Haaswijk

Due to recent advances, constraint solvers have become efficient tools for synthesizing optimum Boolean circuits. We take advantage of this by showing how SAT based exact synthesis may be used as a method for finding minimum length Boolean chains. As oppos ...

IEEE2017

Exact Synthesis of Majority-Inverter Graphs and Its Applications

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Mathias Soeken, Luca Gaetano Amarù

We propose effective algorithms for exact synthesis of Boolean logic networks using satisfiability modulo theories (SMT) solvers. Since exact synthesis is a difficult problem, it can only be applied efficiently to very small functions, having up to 6 varia ...

Ieee-Inst Electrical Electronics Engineers Inc2017

Exploiting Satisfiability Solvers for Efficient Logic Synthesis

Ana Petkovska

Logic synthesis is an important part of electronic design automation (EDA) flows, which enable the implementation of digital systems. As the design size and complexity increase, the data structures and algorithms for logic synthesis must adapt and improve ...

EPFL2017

A Compiler for Parallel and Resource-Constrained Programmable in-Memory Computing

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Mathias Soeken, Giulia Meuli

Solid-state resistive switches have recently enabled low-power, scalable, non-volatile memories. Their proven intrinsic logic operation, allowing design of in-memory computing systems, attracted the attention of the research community. A Programmable Logic ...

2017

A Sound and Complete Axiomatization of Majority-n Logic

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

Manipulating logic functions via majority operators recently drew the attention of researchers in computer science. For example, circuit optimization based on majority operators enables superior results as compared to traditional logic systems. Also, the B ...

Institute of Electrical and Electronics Engineers2016

New Data Structures and Algorithms for Logic Synthesis and Verification

Luca Gaetano Amarù

The strong interaction between Electronic Design Automation (EDA) tools and Complementary Metal-Oxide Semiconductor (CMOS) technology contributed substantially to the advancement of modern digital electronics. The continuous downscaling of CMOS Field Effec ...

EPFL2015

Ultra low power NEMFET based logic

Mihai Adrian Ionescu, Antonios Bazigos, Surya Shankar Dan

In this paper, we introduce a Nano-Electro-Mechanical Field Effect Transistor (NEMFET) based logic family tailored to the implementation of low speed and ultra low energy functional units and processors. Basic Boolean gates implemented with NEMFETs only ar ...

IEEE2013

Supercriticality of an annealed approximation of Boolean networks

Thomas Mountford, Daniel Rodrigues Valesin

We consider a model recently proposed by Chatterjee and Durrett [1] as an "annealed approximation" of boolean networks, which are a class of cellular automata on a random graph, as defined by S. Kauffman [5]. The starting point is a random directed graph o ...

Univ Washington, Dept Mathematics2013

Cryptographic protocol logic: Satisfaction for (timed) Dolev-Yao cryptography

Simon Kramer

This article is about a breadth-first exploration of logical concepts in cryptography and their linguistic abstraction and model-theoretic combination in a comprehensive logical system, called CPL (for Cryptographic Protocol Logic). We focus on two fundame ...

2008

Fault-Tolerant Logic Gates Using Neuromorphic CMOS Circuits

Yusuf Leblebici, Alexandre Schmid, Neil Joye

Fault-tolerant design methods for VLSI circuits, which have traditionally been addressed at system level, will not be adequate for future very-deep submicron CMOS devices where serious degradation of reliability is expected. Therefore, a new design approac ...

IEEE2007

Étude du tomographe de haute résolution pour petits animaux ClearPET par la méthode de Monte Carlo

Martin Rey

The Lausanne ClearPET demonstrator is one of the new generation of high resolution small animal PET scanners. A high resolution PET scanner aims to maximize the signal-to-noise ratio measured in pixels for a given time without compromising spatial resoluti ...

EPFL2007

Plasticity of functional connectivity in the adult spinal cord

Grégoire Courtine

This paper emphasizes several characteristics of the neural control of locomotion that provide opportunities for developing strategies to maximize the recovery of postural and locomotor functions after a spinal cord injury (SCI). The major points of this p ...

2006