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Concept

Jitter

Related publications (16)

Doping Engineering for PDP Optimization in SPADs Implemented in 55-nm BCD Process

Edoardo Charbon, Claudio Bruschini, Myung Jae Lee, Wenfeng Liu

We introduce a new family of single-photon avalanche diodes (SPADs) with enhanced depletion regions in a 55-nm Bipolar-CMOS-DMOS (BCD) technology. We demonstrate how to systematically engineer doping profiles in the main junction and in deep p-well layers ...

Ieee-Inst Electrical Electronics Engineers Inc2024

Analysis of Dampers in Time-Sensitive Networks With Non-Ideal Clocks

Jean-Yves Le Boudec, Ehsan Mohammadpour

Dampers are devices that reduce delay jitter in the context of time-sensitive networks, by delaying packets for the amount written in packet headers. Jitter reduction is required by some real-time applications; beyond this, dampers have the potential to so ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

A Low-Jitter and Low-Spur Charge-Sampling PLL

Edoardo Charbon

This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing an ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

A 10-to-12 GHz 5mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur

Edoardo Charbon

This paper presents a charge-sampling PLL (CSPLL), that demonstrates the best reported jitter-power FOM of -258.9 dB thanks to its high phase-detection gain and to the removal of the power-hungry buffer driving the phase detector. It also achieves -65 dBc ...

IEEE2020

Spatial covariance improves BCI performance for late ERPs components with high temporal variability

José del Rocio Millán Ruiz, Ricardo Andres Chavarriaga Lozano, Lucian Andrei Gheorghe, Marija Uscumlic, Ruslan Aydarkhanov

Objective. Event Related Potentials (ERPs) reflecting cognitive response to external stimuli, are widely used in brain computer interfaces. ERP waveforms are characterized by a series of components of particular latency and amplitude. The classical ERP dec ...

2020

A 60 Gb/s 1.9 pJ/bit NRZ Optical-Receiver with Low Latency Digital CDR in 14nm CMOS FinFET

Yusuf Leblebici, Alessandro Cevrero, Thomas Toifl, Lukas Kull, Ilter Ozkaya

This work reports a low power implementation of a 60Gb/s NRZ optical receiver (RX) in 14nm bulk CMOS finFET featuring a first-order digital CDR with high jitter tolerance (JTOL). The design includes a single phase-rotator (PR) with low complexity control l ...

2017

Jitter Analysis and Measurement in Subthreshold Source-Coupled Differential Ring Oscillators

Yusuf Leblebici, Mahsa Shoaran, Seyed Armin Tajalli

The jitter and the phase noise of ring oscillators utilizing subthreshold source-coupled logic (STSCL) style are analyzed in this paper. Closed-form equations are derived to predict the jitter and phase noise caused by white and flicker noise. Measurement ...

2015

Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits

Yusuf Leblebici, Alexandre Schmid, Mahsa Shoaran, Seyed Armin Tajalli

This article explores the effect of device parameter variations on the performance of subthreshold source-coupled logic (STSCL) circuits. A test chip has been fabricated in a standard CMOS 90 nm technology to study the matching properties of STSCL circuits ...

2015

Exploiting the Path Propagation Time Differences in Multipath Transmission with FEC

Maciej Kurant

We consider a transmission of a delay-sensitive data stream (e. g., a video call) from a single source to a single destination. The reliability of this transmission may suffer from bursty packet losses - the predominant type of failures in today's Internet ...

2011

High Performance InP-Based Quantum Dash Semiconductor Mode-Locked Lasers for Optical Communications

Several applications are pushing the development of high performance mode-locked lasers: generation of short pulses for extremely high bit rate transmission at 100 Gb/s and beyond, all-optical clock recovery at 40 Gb/s and beyond, generation of millimeter ...

2009

Exploiting the Path Propagation Time in Multipath Transmission with FEC

We consider a transmission of a delay-sensitive data stream from a single source to a single destination. The reliability of this transmission may suffer from bursty packet losses - the predominant type of failures in today's Internet. An effective and wel ...

2009

A Power-Efficient Clock and Data Recovery Circuit in 0.18-um CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

Yusuf Leblebici, Seyed Armin Tajalli, Paul Victor Georges Muller

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two ma ...

2007

Tradeoffs in Design of Low-Power Gated-Oscillator CDR Circuits

Yusuf Leblebici, Seyed Armin Tajalli, Paul Victor Georges Muller

This article describes some techniques for implementing low- power clock and data recovery (CDR) circuits based on gated- oscillator (GO) topology for short distance applications. Here, the main tradeoffs in design of a high performance and power-efficient ...

2007

Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini

On-chip wires are becoming unreliable as the effect of various noise sources increases with technology scaling. This leads to unpredictable timing delay variations on the interconnect wires. There is a significant need to mitigate the effect of parasitics ...

2006

A delay optimal policy for symmetric broadcast channels

Stéphane Musy

We consider the rate allocation problem when two users (each one associated with one receiver) send packets through a symmetric broadcast channel. Under the assumption that the packet lengths are exponentially distributed, we establish the delay optimality ...

2006

Jitter Tolerance Analysis of Clock and Data Recovery Circuits using Matlab and VHDL-AMS

Yusuf Leblebici, Paul Victor Georges Muller

In the scope of the development of a complete top-down design flow targeting clock and data recovery circuits for high-speed data links, we present two methods to analyze the jitter tolerance of such links, based on statistical simulation of incoming data ...

2005