Concept

Logic simulation

Related publications (25)

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

Spatial Modeling for Building Design Evaluation: from Visual Landscape Quality Assessment to Devaluation Risk Estimation

Adam Robert Swietek

Zoning reform is a crucial tool for cities to adapt to contemporary challenges. However, its implementation remains challenging. Property owners, with a vested interest in the value of their neighborhoods, are sensitive to local developments and the potent ...

EPFL2024

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

Analytic modelling of passive microfluidic mixers

Jean-Michel Sallese

This paper deals with a new analytical model for microfluidic passive mixers. Two common approaches already exist for such a purpose. On the one hand, the resolution of the advection-diffusion-reaction equation (ADRE) is the first one and the closest to ph ...

AMER INST MATHEMATICAL SCIENCES-AIMS2022

High-Level Synthesis of Dynamically Scheduled Circuits

Lana Josipovic

High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. These tools almost universally build datapaths that are controlled using a centralized controller which relies on a static, compile-time schedule to determine ...

EPFL2021

Simulation of CMOS APS Operation and Crosstalk in SPICE With Generalized Devices

Jean-Michel Sallese, Chiara Rossi

We present SPICE simulations of a CMOS APS pixel element consisting of the optical sensor with the sensing circuit. The photodiode is simulated at the physics level by means of the so-called Generalized Devices, without any predefined compact model. Conver ...

2020

Electromagnetic Time Reversal: Theory, Application to Fault Location in Power Networks and Experimental Validation

Zhaoyang Wang

The time-reversal invariance is readily described and universally embodied in most laws of nature, either in a strict or in a soft sense. Based on this underlying physical principle, time-reversal theory has been theoretically and experimentally studied in ...

EPFL2020

Finding a Needle in the Haystack of Hardened Interconnect Patterns

Paolo Ienne, Grace Zgheib, Stefan Nikolic

Circuits naturally exhibit recurring patterns of local interconnect. Hardening those patterns when designing Field Programmable Gate Array (FPGA) clusters can both eliminate slow programmable connections from the critical path and remove the need for trans ...

IEEE2019

Outdoor comfort simulation of complex architectural designs: a review of simulation tools from the designer perspective

Jean-Louis Scartezzini, Silvia Coccolo, Emanuele Naboni

The expanding design interest in outdoor comfort design is today supported by a few software tools. Given their different user-friendliness, modelling environments and simulation engines, a rational inquiry is how they are integrated into the digital desig ...

2018

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin

This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. In contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circ ...

ACM2016

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Andreas Peter Burg, Jeremy Hugues-Felix Constantin, Georgios Karakonstantis

This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. hi contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circ ...

Ieee2016

Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

A 3-D simulation of substrate currents is crucial to analyze parasitic coupling effects due to minority carrier injection in smart power ICs. In this paper, a substrate parasitic extraction methodology is introduced by dividing the IC layout into elementar ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Automatic Generation of Efficient Accelerators for Reconfigurable Hardware

Christos Kozyrakis

Acceleration in the form of customized datapaths offer large performance and energy improvements over general purpose processors. Reconfigurable fabrics such as FPGAs are gaining popularity for use in implementing application-specific accelerators, thereby ...

Ieee2016

Fast Simulation of Electromagnetic Transients in Power Systems : Numerical Solvers and their Coupling with the Electromagnetic Time Reversal Process

Reza Razzaghi

The development of modern and future power systems is associated with the definition of new approaches for their simulation, control, and protection. To give an example, the increasing connection of massive renewable energy conversion systems is justifying ...

EPFL2016

System Design Automation: Challenges and Limitations

Joseph Sifakis

Electronic design automation (EDA) has enabled the integrated circuit industry to sustain exponentially increasing product complexity growth until today, while maintaining consistent product development timeline and costs. We argue that the success of EDA- ...

Ieee-Inst Electrical Electronics Engineers Inc2015

Parametric scripting for early design performance simulation

Guillaume Labelle

This paper discusses the advantages of using a coding interface both to describe form and run performance simulations in the context of architectural design. It outlines the relevance of combining recent interest in the design community for parametric scri ...

Elsevier Science Sa2014

Nanowire systems: technology and design (invited paper)

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Davide Sacchetto, Luca Gaetano Amarù, Michele De Marchi, Shashi Kanth Bobba

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this work, we consider double independent gate, vertically-stacked nanowire FETs with gate-all-around structures and typical diameter of 20-nm. These devices, which we hav ...

Royal Soc2014

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Giovanni De Micheli, Yusuf Leblebici, Alessandro Cevrero, Giulia Beanato

3D-ICs based on TSV technology provide high bandwidth inter-chip connections. The drawback is that most of the existing TSVs consume a large amount of silicon real estate. We present circuit-level design and analysis of area efficient, low power, high-data ...

2014

Limits to high-speed simulations of spiking neural networks using general-purpose computers

Wulfram Gerstner, Friedemann Zenke

To understand how the central nervous system performs computations using recurrent neuronal circuitry, simulations have become an indispensable tool for theoretical neuroscience. To study neuronal circuits and their ability to self-organize, increasing att ...

Frontiers Research Foundation2014

A simulation-optimization approach to deploy Internet services in large-scale systems with user-provided resources

Julia Proskurnia

Cloud computing systems can benefit from the use of personal and non-dedicated computers, which are currently employed in volunteer computing systems. Being non-dedicated, these resources show random behavior regarding the times they are online (available) ...

Sage Publications Ltd2014