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Laboratoire de nanophotonique et d'optoélectronique intégré

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Publications associées (28)

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Publications associées (28)

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InAs-on-Insulator Fin Nanostructures for Integrated Computation and Sensing Functions

Maneesha Rupakula

Field-effect transistors (FETs) have established themselves as a leading platform for electrical detection of chemical and biological species. Their advantages over other optical, mechanical sensing platforms are attributed to being miniaturizable, mechani ...

EPFL2020

Exploration of Negative Capacitance Devices and Technologies

Ali Saeidi

Conventional device scaling has been the main guiding principle of the MOS device engineering over these past years. However, this aggressive scaling would be eventually limited due to the inability to remove the heat generated by MOSFET devices. The power ...

EPFL2019

Polarity-Controllable Devices and Circuits for Doping-Free 2D Electronics

Giovanni Vincenzo Resta

The growth of information technology has been sustained by the miniaturization of Complementary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors (FETs), with the number of devices per unit area constantly increasing, as exemplified by Mooreâ s la ...

EPFL2019

High-performance normally-off tri-gate GaN power MOSFETs

Elison de Nazareth Matioli, Jun Ma, Luca Nela, Minghua Zhu

In this work, we present the investigation of the combination of gate recess and tri-gate structures to achieve high performance normally-off GaN-on-Si MOSFETs with high positive threshold voltage ( VTH ), low specific on resistance ( RON,SP ) and high out ...

IEEE2019

On the Dynamic Performance of Laterally Gated Transistors

Elison de Nazareth Matioli, Armin Jafari, Mohammad Samizadeh Nikooytabalvandani, Catherine Erine, Giovanni Santoruvo

Laterally gated transistors have been proposed as an innovative device architecture in which a semiconducting channel is controlled by side gates. In this sense, the gate can either be in contact with the sidewalls or be separated by a gap. In the latter c ...

Institute of Electrical and Electronics Engineers2019

Sub-Thermionic Scalable III-V Tunnel Field-Effect Transistors Integrated on Si (100)

Mihai Adrian Ionescu, Kirsten Emilie Moselund

We present scalable III-V heterojunction tunnel FETs fabricated using a Si CMOS-compatible FinFET process flow and integrated on Si (100) substrates. The tunneling junction is fabricated through self-aligned selective p(+) GaAsSb raised source epitaxial re ...

IEEE2019

Doping-Free Complementary Logic Gates Enabled by Two-Dimensional Polarity-Controllable Transistors

Giovanni De Micheli, Giovanni Vincenzo Resta, Pierre-Emmanuel Julien Marc Gaillardon

Atomically thin two-dimensional (2D) materials belonging to transition metal dichalcogenides, due to their physical and electrical properties, are an exceptional vector for the exploration of next-generation semiconductor devices. Among them, due to the po ...

2018

The Cryogenic Temperature Behavior of Bipolar, MOS, and DTMOS Transistors in Standard CMOS

Edoardo Charbon

Both CMOS bandgap voltage references and temperature sensors rely on the temperature behavior of either CMOS substrate BJTs or MOS transistors in weak inversion. Bipolar transistors are generally preferred over MOS transistors because of their lower spread ...

2018