Publication

Methodology and Technique to Improve Throughput of FPGA-based CAL Dataflow Programs: Case Study of the RVC MPEG-4 SP Intra Decoder

Publications associées (31)

Real-time actuation of a dielectric elastomer actuator neuroprosthesis for facial paralysis

Yves Perriard, Yoan René Cyrille Civet, Thomas Guillaume Martinez, Stefania Maria Aliki Konstantinidi, Armando Matthieu Walter, Amine Benouhiba

Facial paralysis is a highly burdening condition, resulting in a patient's inability to move his mimic musculature on one or both sides of his face. This condition compromises the patient's communication and facial expressions, and thus dramatically reduce ...

2023

Exploring the effectiveness of using internal CNC system signals for chatter detection in milling process

Dimitrios Kyritsis, Roberto Pérez, Xiaochen Zheng

Chatter is a harmful self-excited vibration that commonly occurs during milling processes. Data -driven chatter detection and prediction is critical to achieve high surface quality and process efficiency. Most existing chatter detection approaches are base ...

ACADEMIC PRESS LTD- ELSEVIER SCIENCE LTD2023

Vibrational NDT with Under-sampled Data through Physics-informed Neural Networks

Olga Fink

The vibrational response of solid materials and structural components is substantially governed by their mechanical and geometrical properties. Low-frequency vibrations and modal frequencies are sensitive to global geometrical deviations, while high-freque ...

2023

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Writing and optimizing application software for heterogeneous platforms including GPU units is a very difficult task that requires designer efforts and resources to consider several key elements to obtain good performance. Dataflow programming has shown to ...

2022

Inter-actions parallel execution on GPU from high-level dataflow synthesis

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Recent GPU architectures make available numbers of parallel processing units that exceed by orders of magnitude the ones offered by CPU architectures. Whereas programs written using dataflow programming languages are well suited for programming heterogeneo ...

IEEE2022

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

Mirjana Stojilovic, David Dervishi, Dina Gamaleldin Ahmed Shawky Mahmoud

Field-programmable gate arrays (FPGAs) combine hardware reconfigurability with a high degree of parallelism. Consequently, FPGAs offer performance gains and power savings for many applications. A recent trend has been to leverage the hardware versatility o ...

2022

Efficient Analytical Query Processing on CPU-GPU Hardware Platforms

Periklis Chrysogelos

Timely insights lead to business growth and scientific breakthroughs but require analytical engines that cope with the ever-increasing data processing needs. Analytical engines relied on rapid CPU improvements, yet the end of Dennard scaling stopped the fr ...

EPFL2022

Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Developing and fine-tuning software programs for heterogeneous hardware such as CPU/GPU processing platforms comprise a highly complex endeavor that demands considerable time and effort of software engineers and requires evaluating various fundamental comp ...

MDPI2022

From C/C plus plus Code to High-Performance Dataflow Circuits

Paolo Ienne, Lana Josipovic, Andrea Guerrieri

High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis

Paolo Ienne, Lana Josipovic

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network Execution

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

The performance of programs executed on heterogeneous parallel platforms largely depends on the design choices regarding how to partition the processing on the various different processing units. In other words, it depends on the assumptions and parameters ...

MDPI2022