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FPGA implementation of Viterbi decoders for MIMO-BICM

Publications associées (29)

Relaxed Locally Correctable Codes With Nearly-Linear Block Length And Constant Query Complexity

Locally correctable codes (LCCs) are error correcting codes C : \Sigmak \rightarrow \Sigman which admit local algorithms that correct any individual symbol of a corrupted codeword via a minuscule number of queries. For systematic codes, this notion is stro ...

SIAM PUBLICATIONS2022

Dynamic SCL Decoder With Path-Flipping for 5G Polar Codes

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Chuan Zhang, Yifei Shen

Since polar were ratified as part of the 5G standard, low-complexity polar decoders with close-to-optimum error-rate performance have received significant attention. Compared to successive cancellation (SC) decoding, both SC list and SC flip decoding can i ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

On the Efficiency of Polar-Like Decoding for Symmetric Codes

Rüdiger Urbanke, Kirill Ivanov

The recently introduced polar codes constitute a breakthrough in coding theory due to their capacity-achieving property. This goes hand in hand with a quasilinear construction, encoding, and successive cancellation list decoding procedures based on the Plo ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Secret Key Generation Using Short Blocklength Polar Coding Over Wireless Channels

Yanina Yurina Shkel

This paper investigates the problem of secret key generation from correlated Gaussian random variables in the short blocklength regime. Short blocklengths are commonly employed in massively connected IoT sensor networks in 5G and beyond wireless systems. P ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

List Ordered Statistics Decoders for Polar Codes

Andreas Peter Burg, Chuan Zhang, Yifei Shen

The de-facto standard decoding algorithm for polar codes, successive cancellation list (SCL) decoding, is a breadth-first search algorithm. By keeping a list of candidate codewords, SCL decoding improves the performance as the list size L increases. Howeve ...

IEEE2022

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

Mirjana Stojilovic, David Dervishi, Dina Gamaleldin Ahmed Shawky Mahmoud

Field-programmable gate arrays (FPGAs) combine hardware reconfigurability with a high degree of parallelism. Consequently, FPGAs offer performance gains and power savings for many applications. A recent trend has been to leverage the hardware versatility o ...

2022

Fast Sequence Repetition Node-Based Successive Cancellation List Decoding for Polar Codes

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Chuan Zhang, Andreas Toftegaard Kristensen, Yifei Shen, Yuqing Ren

Compared with the bit-wise successive cancellation list (SCL) decoding of polar codes, the node-based Fast SCL decoding significantly reduces the decoding latency by identifying special constituent codes and decoding these in parallel. To further reduce th ...

IEEE2022

FPGA-to-CPU Undervolting Attacks

Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud

FPGAs are proving useful and attractive for many applications, thanks to their hardware reconfigurability, low power, and high-degree of parallelism. As a result, modern embedded systems are often based on systems-on-chip (SoCs), where CPUs and FPGAs share ...

IEEE2022

Decentralized in-order execution of a sequential task-based code for shared-memory architectures

Charly Nicolas Lucien Castes

The hardware complexity of modern machines makes the design of adequate programming models crucial for jointly ensuring performance, portability, and productivity in high-performance computing (HPC). Sequential task-based programming models paired with adv ...

IEEE COMPUTER SOC2022