Run-time Mapping of Applications on FPGA-based Reconfigurable Systems

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Embedded systems confront two opposite goals: low-power operation and high performance. The current trend to reach these goals is toward heterogeneous platforms, including multi-core architectures with heterogeneous cores and hardware accelerators. The lat ...

Fuzzing reliably and efficiently finds bugs in software, including operating system kernels. In general, higher code coverage leads to the discovery of more bugs. This is why most existing kernel fuzzers adopt strategies to generate a series of inputs that ...

Vision systems built around conventional image sensors have to read, encode and transmit large quantities of pixel information, a majority of which is redundant. As a result, new computational imaging sensor architectures were developed to preprocess the r ...

Field-programmable gate arrays (FPGAs) combine hardware reconfigurability with a high degree of parallelism. Consequently, FPGAs offer performance gains and power savings for many applications. A recent trend has been to leverage the hardware versatility o ...

FPGAs are proving useful and attractive for many applications, thanks to their hardware reconfigurability, low power, and high-degree of parallelism. As a result, modern embedded systems are often based on systems-on-chip (SoCs), where CPUs and FPGAs share ...

Counting single photons and measuring their arrival time is of crucial importance for imaging and quantum applications that use single photons to outperform classical techniques. The investigation of the coincidence, i.e. correlation, between photons can b ...

Model compression techniques have lead to a reduction of size and number of computations of Deep Learning models. However, techniques such as pruning mostly lack of a real co-optimization with hardware platforms. For instance, implementing unstructured pru ...

The MALTA pixel chip is a 2 cm x 2 cm large monolithic pixel detector developed in the Tower 180 nm imaging process. The chip contains four CMOS transceiver blocks at its sides which allow chip-to-chip data transfer. The power pads are located mainly at th ...

Flow cell arrays (FCAs) concurrently provide efficient on-chip liquid cooling and electrochemical power generation. This technology is especially promising for three-dimensional multi-processor systems-on-chip (3D MPSoCs) realized in deeply scaled technolo ...

Applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on FPGAs due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by re ...

Run-time Mapping of Applications on FPGA-based Reconfigurable Systems

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Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

ACTOR: Action-Guided Kernel Fuzzing

Computational Imaging SPAD Cameras

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

FPGA-to-CPU Undervolting Attacks

Assessment of the Bundle SNSPD Plus FPGA-Based TDC for High-Performance Time Measurements

Structured and tiled-based pruning of Deep Learning models targeting FPGA implementations

Development of a large-area, light-weight module using the MALTA monolithic pixel detector

Thermal and Voltage-Aware Performance Management of 3D MPSoCs with Flow Cell Arrays and Integrated SC Converters

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs