Performance Comparison of Analog and Digital Implementations of a Synchronous Rectification Method for 6.78 MHz Applications

Synchronous rectification is a well-established technique at low frequencies for reducing the conduction losses of conventional diode-based rectifiers. However, as switching frequencies increase, several challenges arise, particularly related to propagation delays and timing accuracy, which directly contribute to increased switching losses. Furthermore, in class-DE rectifiers, adaptive dead-time is essential to ensure zero-voltage switching across the load range. A novel synchronous rectification method was previously presented that addresses propagation delays by using a PLL and includes load-adaptive dead-time, thereby enabling zero-current and zero-voltage switching. In this paper, a new digital FPGA-based method’s implementation is compared with the previously developed analog counterpart. The performance comparison focuses on adaptive dead-time matching and its impact on third-quadrant losses, as well as on the method’s dynamic response to load variations and its robustness under frequency-drift conditions. The performance comparison is supported by the experimental validation of two built GaN-based half-bridge prototypes.