Publication

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster

Publications associées (31)

Dimensionally Engineered Perovskite Heterostructure for Photovoltaic and Optoelectronic Applications

Mohammad Khaja Nazeeruddin, Yonghui Lee, Kyung Taek Cho, Sanghyun Paek

Although 2D|3D has shown potential for application in multifunctional devices, the principle of operation for multifunction devices (SOLAR Cell-LED: SOLED) has not yet been revealed. However, most studies have reported that the devices have only one auspic ...

2019

Learning-Based Hardware Design for Data Acquisition Systems

Cosimo Aprile

This multidisciplinary research work aims to investigate the optimized information extraction from signals or data volumes and to develop tailored hardware implementations that trade-off the complexity of data acquisition with that of data processing, conc ...

EPFL2018

Hardware / Software Architectural and Technological Exploration for Energy-Efficient and Reliable Biomedical Devices

Loris Gérard Duch

Nowadays, the ubiquity of smart appliances in our everyday lives is increasingly strengthening the links between humans and machines. Beyond making our lives easier and more convenient, smart devices are now playing an important role in personalized health ...

EPFL2018

A Machine Learning-Based Strategy for Efficient Resource Management of Video Encoding on Heterogeneous MPSoCs

David Atienza Alonso, William Andrew Simon, Marina Zapater Sancho, Arman Iranfar

The design of new streaming systems is becoming a major area of research to deploy services targeted in the Internet-of-Things (IoT) era. In this context, the new High Efficiency Video Coding (HEVC) standard provides high efficiency and scalability of qual ...

2018

Trading off Energy versus Accuracy in Modern Computing Systems : From Digital Circuit Design to Programming Techniques

Jérémy Lucien Maurice Schlachter

The slowdown of Moore's law, which has been the driving force of the electronics industry over the last 5 decades, is causing serious problem to Integrated Circuits (ICs) improvements. Technology scaling is becoming more and more complex and fabrication co ...

EPFL2018

Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis

Christian Enz, Vincent Frédéric Camus, Mattia Cacciotti, Jérémy Lucien Maurice Schlachter, Alessandro Pezzotta

In this paper, the hardware acceleration of a tone-mapping algorithm for High-Dynamic-Range image processing is presented. Starting from the C++ source code, High-Level Synthesis has been performed using Xilinx SDSoC for a Xilinx Zynq SoC device. After an ...

IEEE2018

PowerCool: Simulation of Cooling and Powering of 3D MPSoCs with Integrated Flow Cell Arrays

David Atienza Alonso, Mohamed Mostafa Sabry Aly, Arvind Raj Mahankali Sridhar, Bruno Michel, Artem Andreev, Marina Zapater Sancho

Integrated Flow-Cell Arrays (FCAs) represent a combination of integrated liquid cooling and on-chip power generation, converting chemical energy of the flowing electrolyte solutions to electrical energy. The FCA technology provides a promising way to addre ...

Institute of Electrical and Electronics Engineers2017

Abstracting Multi-Core Topologies with MCTOP

Rachid Guerraoui, Vasileios Trigonakis, Georgios Chatzopoulos

Portability and efficiency are usually antagonists in multi-core computing. In order to develop efficient code, one needs to take into account the topology of the target multi-cores (e.g., for locality). This clearly hampers code portability. In this paper ...

ACM Press2017

A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache

Giovanni De Micheli, Luca Benini

The use of multi-core clusters is a promising option for data-intensive embedded applications such as multi-modal sensor fusion, image understanding, mobile augmented reality. In this paper, we propose a power-efficient 3-D on-chip interconnect for multi-c ...

IEEE2016

Towards Scalable Synchronization on Multi-Cores

Vasileios Trigonakis

The shift of commodity hardware from single- to multi-core processors in the early 2000s compelled software developers to take advantage of the available parallelism of multi-cores. Unfortunately, only few---so-called embarrassingly parallel---applications ...

EPFL2016

Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays

Paolo Ienne, Sadegh Yazdanshenas, Hossein Asadi

Nanoelectromechanical (NEM) relays are a promising emerging technology that has gained widespread research attention due to its zero leakage current, sharp ON-OFF transitions, and complementary metal-oxide-semiconductor compatibility. As a result, NEM rela ...

Institute of Electrical and Electronics Engineers2016