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FD SOI Hall sensor electronics interfaces for energy measurement

Publications associées (31)

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This article describes the design and the characterization of the ANTIGONE (ANalog To dIGital cONvErter) ASIC (Application Specific Integrated Circuit) built in AMS 0.35 m technology for low dc-current sensing. This energy-efficient ASIC was specifically d ...

2021

High-Speed ADC Design and Optimization for Wireline Links

Ayça Akkaya

The ever-growing global internet traffic has increased demand for higher speed data transmission. As the bandwidth requirements of wireline links increase, extensive digital equalization techniques are required to compensate for the high-frequency channel ...

EPFL2021

A Pixel Design of a Branching Ultra-Highspeed Image Sensor

Edoardo Charbon

A burst image sensor named Hanabi, meaning fireworks in Japanese, includes a branching CCD and multiple CMOS readout circuits. The sensor is backside-illuminated with a light/charge guide pipe to minimize the temporal resolution by suppressing the horizont ...

2021

Nanowatt Acoustic Inference Sensing Exploiting Nonlinear Analog Feature Extraction

Christian Enz, Minhao Yang, Jun Zhang

Ultralow-power sensing with inference functionality embedded in sensor nodes is essential for enabling the emerging pervasive intelligence. For acoustic inference sensing, the feature extraction can take advantage of power-efficient analog circuits. Howeve ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Blumino: The First Fully Integrated Analog SiPM With On-Chip Time Conversion

Edoardo Charbon, Andrei Ardelean, Andrada Alexandra Muntean, Esteban Venialgo Araujo, Emanuele Ripiccini

Blumino is the first analog silicon photomultiplier with integrated amplifier, comparator and time-to-digital converter (TDC). The combination of a photodetector together with on-chip readout circuitry enables system-level advantages, such as internal para ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

A 32 Gb/s PAM-16 TX and ADC-Based RX AFE with 2-tap embedded analog FFE in 28 nm FDSOI

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This paper presents a 32 Gb/s 16-level pulse amplitude modulation (PAM-16) source-series-terminated transmitter (TX) and a receiver (RX) analog front-end (AFE) in 28 nm FDSOI. The 8-way time-interleaved successive-approximation register (SAR) analog-to-dig ...

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Energy-Efficient Design Techniques for High-Speed Wireline Serial Links

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The exponential growth in computing power and multimedia services has caused a tremendous increase in data traffic in recent years. This increase in data traffic brings a strong demand for data bandwidth of electrical input/output (I/O) links and pushes th ...

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Capacitive sensor to monitor the level of drug inside an injector pen

Sylvain Paul Fernand Joly

Diabete is a disease which is spreading faster than ever, impacting now a larger population. Patients suffering from this disease need the injection of insulin to control extracellular sugar levels. Pharmaceutical companies developed injector pens to allow ...

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Asynchronous sar adc with unit length capacitors and constant common mode monotonic switching

Volkan Cevher, Arda Uran

A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) comprising a Track-and-Hold (T/H) switch configured for a sampling of an input voltage in the form of charge onto a capacitor; a Capacitive Digital-to- Analog Converter (CD AC) opera ...

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Cryogenic MOSFET Modeling for Large-Scale Quantum Computing

Arnout Lodewijk M Beckers

Promising results of state-of-the-art quantum computers fuel a world-wide effort in academic and private research laboratories to scale up the number of qubits and improve their characteristics in large arrays. To meet the scale-up challenge, innovative mi ...

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An 8-Bit 800 MS/s Loop-Unrolled SAR ADC With Common-Mode Adaptive Background Offset Calibration in 28 nm FDSOI

Yusuf Leblebici, Ayça Akkaya, Firat Çelik

This paper presents a low-power single-channel 8-bit loop-unrolled (LU) successive approximation register (SAR) analog-to-digital-converter (ADC) with a novel common-mode adaptive background comparator offset calibration scheme. LU-SAR ADCs use multiple co ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021