Receiver design for multi-antenna wireless communications

Algorithm choices and corresponding VLSI architectures for spatial multiplexing receivers in multiple-input multiple-output (MIMO) communication systems are described in this paper. Implementations of linear and successive interference cancellation receivers are compared to implementations of maximum likelihood (ML) decoders that attain optimum bit error rate performance. The presented designs provide reference for the true silicon complexity of the algorithms under consideration and help to identify the limits with respect to practical implementations.