LUT-Based Optimization For ASIC Design Flow

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Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

Modern integrated circuits are tiny yet incredibly complex technological artifacts, composed of millions and billions of individual structures working in unison. Managing their complexity and facilitating their design drove part of the co-evolution of mode ...

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

The pervasive adoption of field-programmable gate arrays (FPGAs) in both cyber-physical systems and the cloud has raised many security issues. Being integrated circuits, FPGAs are susceptible to fault and power side-channel attacks, which require physical ...

Cloud computing environments increasingly provision FPGAs because of their fine-grained, highly parallel, and flexible hardware architecture. The availability of FPGAs in the cloud fueled research on the security risks associated with exposing FPGA fabric ...

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

Machine learning and data processing algorithms have been thriving in finding ways of processing and classifying information by exploiting the hidden trends of large datasets. Although these emerging computational methods have become successful in today's ...

Three-Dimensional Multi-Processor Systems-on-Chip (3D MPSoCs) are promising solutions for highly intensive Artificial Intelligence (AI) and Big Data applications. They combine remarkably dense computation capabilities and massive communication bandwidths. ...

Individual transistors based on emerging reconfigurable nanotechnologies exhibit electrical conduction for both types of charge carriers. These transistors (referred to as Reconfigurable Field-Effect Transistors (RFETs)) enable dynamic reconfiguration to d ...

Approximate logic synthesis is an emerging field that tolerates errors in the synthesized logic circuits for better optimization quality. Indeed, in many computing problems, the requirement of preserving the exact functionality either results in unnecessar ...

In this work, we develop timing-driven CAD support for FPGA architectures with direct connections between LUTs. We do so by proposing an efficient ILP-based detailed placer, which moves a carefully selected subset of LUTs from their original positions, so ...

Flow Cell Arrays (FCA) technology employs microchannels filled with an electrolytic fluid to concurrently provide cooling and power generation to integrated circuits (ICs). This solution is particularly appealing for Three-Dimensional Multi-Processor Syste ...

Side-channel CPU disassembly is a side-channel attack that allows an adversary to recover instructions executed by a processor. Not only does such an attack compromise code confidentiality, it can also reveal critical information on the system’s internals. ...

The increasing luminosity in HEP (High Energy Physics) colliders demands trigger systems to be more selective. First, more information from the detector is routed to the trigger system. Second, larger parts of this information are processed together. These ...

Despite FPGAs rapidly evolving to support the requirements of the most demanding emerging applications, their high static power consumption, concentrated within the routing resources, still presents a major hurdle for low-power applications. Augmenting the ...

High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. These tools almost universally build datapaths that are controlled using a centralized controller which relies on a static, compile-time schedule to determine ...

Threshold Implementations have become a popular generic technique to construct circuits resilient against power analysis attacks.In this paper, we look to devise efficient threshold circuits for the lightweight block cipher family SKINNY. The only threshol ...

In the last few years, the field of lightweight cryptography has seen an influx in the number of block ciphers and hash functions being proposed. In the past there have been numerous papers that have looked at circuit level implementation of block ciphers ...

Ultralow-power sensing with inference functionality embedded in sensor nodes is essential for enabling the emerging pervasive intelligence. For acoustic inference sensing, the feature extraction can take advantage of power-efficient analog circuits. Howeve ...

LUT-Based Optimization For ASIC Design Flow

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Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Graph generative deep learning models with an application to circuit topologies

Highly Parallel RTL Simulation

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

Design and management of three-dimensional multi-processor systems-on-chip with integrated flow cell arrays

Utilizing XMG-based Synthesis to Preserve Self-Duality for RFET-Based Circuits

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

Detailed Placement for Dedicated LUT-Level FPGA Interconnect

Thermal and Power-Aware Run-Time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays

A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time

Low-Latency High-Bandwidth Circuit and System Design for Trigger Systems in High Energy Physics

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

High-Level Synthesis of Dynamically Scheduled Circuits

Improving First-Order Threshold Implementations of SKINNY

A Deeper Look at the Energy Consumption of Lightweight Block Ciphers

Nanowatt Acoustic Inference Sensing Exploiting Nonlinear Analog Feature Extraction