Publication

Configurable High-Throughput Decoder Architecture for Quasi-Cyclic LDPC Codes

Publications associées (31)

A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS

David Ruffieux, Andreas Peter Burg, Thomas Christoph Müller

Microcontroller systems operating at low supply voltage in near- or sub-threshold regime suffer both from increased effects of PVT (Process, Voltage, Temperature) variation and from a larger share of leakage on overall power due to the reduced frequency. W ...

IEEE2019

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

Christian Enz, Igor Stolichnov, Mihai Adrian Ionescu, Farzan Jazaeri, Ali Saeidi

Boltzmann electron energy distribution poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-source current at 300 K. Neg ...

Nature Research2019

Scalable Synchronization in Shared-Memory Systems: Extrapolating, Adapting, Tuning

Georgios Chatzopoulos

As hardware evolves, so do the needs of applications. To increase the performance of an application, there exist two well-known approaches. These are scaling up an application, using a larger multi-core platform, or scaling out, by distributing work to mul ...

EPFL2018

A Sub-μW/Channel, 16-Channel Seizure Detection and Signal Acquisition SoC Based on Multichannel Compressive Sensing

Alexandre Schmid, Reza Ranjandish

An accurate 16-channel seizure detection system-on-chip is presented, which is based on extracting features from the compressed recorded data using multichannel compressive sensing (MCS). MCS is used to reduce the transmission data rate of sparse biologica ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018

Near-Memory Address Translation

Javier Picorel Obando

Virtual memory (VM) is a crucial abstraction in modern computer systems at any scale, from handheld devices to datacenters. VM provides programmers the illusion of an always sufficiently large and linear memory, making programming easier. Although the core ...

EPFL2017

Fabrication, Characterization and Integration of Resistive Random Access Memories

Jury Sandrini

The functionalities and performances of today's computing systems are increasingly dependent on the memory block. This phenomenon, also referred as the Von Neumann bottleneck, is the main motivation for the research on memory technologies. Despite CMOS tec ...

EPFL2017

Total ionizing dose effects on a 28 nm Hi-K metal-gate CMOS technology up to 1 Grad

Chunmin Zhang, Alessandro Pezzotta

This paper presents the results of an irradiation study on single transistors manufactured in a 28 nm high-k commercial CMOS technology up to 1 Grad. Both nMOSFET and pMOSFET transistors have been irradiated and electrical parameters have been measured. Fo ...

2017

Easy and Accurate Hardware-based Program Performance Monitoring

Andrzej Pawel Nowak

The performance monitoring of computer systems is a complex affair, made even more challenging by the increasing gap between hardware and software. Methods that collect and feed data to performance analysis can usually be classified into one of two groups. ...

EPFL2017

Circuit Design, Architecture and CAD for RRAM-based FPGAs

Xifan Tang

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two ...

EPFL2017

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

Jeremy Hugues-Felix Constantin

With the omnipresence of embedded processing in all forms of electronics today, there is a strong trend towards wireless, battery-powered, portable embedded systems which have to operate under stringent energy constraints. Consequently, low power consumpti ...

EPFL2016

An Ultra-Low Power NVM-Based Multi-Core Architecture for Embedded Bio Signal Processing

David Atienza Alonso, Ruben Braojos Lopez

Healthcare delivery is evolving towards new Wireless Body Sensor Nodes (WBSN), which are miniaturized devices able to acquire, process and transmit subjects’ bio-signals in real time within a tiny energy budget. Recent efforts on AD converters and transmis ...

2016