This thesis studies elastic dataflow as a practical design methodology for FPGA-based digital systems whose performance is increasingly limited by external-memory behavior rather than compute density. Modern FPGA platforms offer abundant logic and on-chip storage, but DDR, HBM, and virtual-memory-backed subsystems impose bandwidth and latency constraints that make memory traffic the dominant bottleneck. In this setting, performance depends not only on data reuse but also on sustaining high memory-level parallelism (MLP), so that many independent requests can overlap and the memory system can reorder, distribute, and coalesce them efficiently. Yet current FPGA design practice remains fragmented: systems are assembled from HLS or RTL kernels, vendor DMA engines and interconnects, and software-visible control interfaces, often introducing brittle orchestration, hidden serialization, and fixed architectural assumptions that limit attainable MLP.
We argue that elastic dataflow is a natural response to these limitations. By relying on local ready/valid handshakes and distributed buffering instead of centralized control and global schedules, elastic designs allow components to make progress whenever their local dependencies are satisfied. With sufficient buffering, elastic pipelines can sustain high throughput despite variable latency, making them well suited to irregular and memory-bound workloads. However, there remains a gap between opaque compiler-driven elastic synthesis and handwritten RTL. This thesis addresses how a slightly higher-level elastic abstraction can improve the design of complex digital systems without sacrificing structural control.
To this end, the thesis introduces Chext, an open-source Chisel-based framework for constructing elastic dataflow circuits and memory-oriented systems. Chext is built around two complementary roles.
First, it provides a structural abstraction for elastic hardware design: reusable, composable primitives; higher-level stateful constructs; flow-level consistency checks; and simulation-time diagnostics that make the dataflow structure explicit while preserving RTL-level control.
Second, Chext serves as an implementation substrate for memory-system architectures that preserve memory-level parallelism through local synchronization, explicit buffering, and decoupled address/payload paths rather than as an automatic performance optimizer. Across the thesis, Chext serves as the implementation substrate for three concrete memory-system contributions: HBMex, which improves HBM throughput for irregular nonbursting accesses; HB-vmem, which scales virtual memory by reusing the hardened HBM interconnect; and FlexiMem, which generates customizable interconnects for virtual memory with tunable address and payload paths fitting the workload demands. Taken together, these results show that elastic dataflow, paired with explicit buffering and memory-aware architectural choices, provides a practical methodology for build
