Impact of body biasing on the retention time of gain-cell memories

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Computing servers play a key role in the development and process of emerging compute-intensive applications in recent years. However, they need to operate efficiently from an energy perspective viewpoint, while maximizing the performance and lifetime of th ...

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Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge

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The growing popularity of edge computing has fostered the development of diverse solutions to support Artificial Intelligence (AI) in energy-constrained devices. Nonetheless, comparatively few efforts have focused on the resiliency exhibited by AI workload ...

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Low-Power Artificial Neural Network Perceptron Based on Monolayer MoS2

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Machine learning and signal processing on the edge are poised to influence our everyday lives with devices that will learn and infer from data generated by smart sensors and other devices for the Internet of Things. The next leap toward ubiquitous electron ...

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Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

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Applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on FPGAs due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by re ...

ASSOC COMPUTING MACHINERY2022

VWR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

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Edge-computing requires high-performance energy-efficient embedded systems. Fixed-function or custom accelerators, such as FFT or FIR filter engines, are very efficient at implementing a particular functionality for a given set of constraints. However, the ...

ASSOC COMPUTING MACHINERY2022

Midas: Systematic Kernel TOCTTOU Protection

Uros Tesic, Mathias Josef Payer, Atri Bhattacharyya

Double-fetch bugs are a plague across all major operating system kernels. They occur when data is fetched twice across the user/kernel trust boundary while allowing concurrent modification. Such bugs enable an attacker to illegally access memory, cause den ...

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An Accuracy-Driven Compression Methodology to Derive Efficient Codebook-Based CNNs

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Codebook-based optimizations are a class of algorithmic-level transformations able to effectively reduce the computing and memory requirements of Convolutional Neural Networks (CNNs). This approach tightly limits the number of unique weights in each layer, ...

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Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

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Even if Dennard scaling came to an end fifteen years ago, Moore' s law kept fueling an exponential growth in compute performance through increased parallelization. However, the performance of memory and, in particular, Dynamic Random Access Memory (DRAM), ...

EPFL2021

Rethinking Software Runtimes for Disaggregated Memory

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Disaggregated memory can address resource provisioning inefficiencies in current datacenters. Multiple software runtimes for disaggregated memory have been proposed in an attempt to make disaggregated memory practical. These systems rely on the virtual mem ...

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Memory chip or memory array for wide-voltage range in-memory computing using bitline technology

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A random access memory having a memory array having a plurality of local memory groups, each local memory group including a plurality of bitcells arranged in a bitcell column, a pair of local bitlines operatively connected to the plurality of bitcells, a p ...

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Software Support for Non-Volatile Memory (NVM) Programming

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Non-Volatile Memory (NVM) is an emerging type of memory device that provides fast, byte-addressable, and high-capacity durable storage. NVM sits on the memory bus and allows durable data structures designs similar to the in-memory equivalent ones. Expensiv ...

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Associativity-agnostic in-cache computing memory architecture optimized for multiplication

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A random access memory array including a plurality of local memory group ways, each local memory group way including, a plurality of local memory groups, each local memory group including, a memory column including a plurality of memory cells, a pair of lo ...

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