Memory chip or memory array for wide-voltage range in-memory computing using bitline technology

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Computing servers play a key role in the development and process of emerging compute-intensive applications in recent years. However, they need to operate efficiently from an energy perspective viewpoint, while maximizing the performance and lifetime of th ...

Modern datacenters host datasets in DRAM to offer large-scale online services with tight tail-latency requirements. Unfortunately, as DRAM is expensive and increasingly difficult to scale, datacenter operators are forced to consider denser storage technolo ...

Analytical engines rely on in-memory caching to avoid disk accesses and provide timely responses by keeping the most frequently accessed data in memory. Purely frequency- & time-based caching decisions, however, are a proxy of the expected query execution ...

Machine learning and signal processing on the edge are poised to influence our everyday lives with devices that will learn and infer from data generated by smart sensors and other devices for the Internet of Things. The next leap toward ubiquitous electron ...

Applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on FPGAs due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by re ...

We have witnessed a wide range of theoretical as well as experimental investigations to envisage external stimuli induced changes in electronic, optical and magnetic properties in the metal organiccomplexes, while hybrid perovskites have recently joined th ...

Computing the count of distinct elements in large data sets is a common task but naive approaches are memory-expensive. The HyperLogLog (HLL) algorithm (Flajolet et al., 2007) estimates a data set's cardinality while using significantly less memory than a ...

The growing popularity of edge computing has fostered the development of diverse solutions to support Artificial Intelligence (AI) in energy-constrained devices. Nonetheless, comparatively few efforts have focused on the resiliency exhibited by AI workload ...

Codebook-based optimizations are a class of algorithmic-level transformations able to effectively reduce the computing and memory requirements of Convolutional Neural Networks (CNNs). This approach tightly limits the number of unique weights in each layer, ...

Long-lasting memories are stored in a small set of neurons scattered throughout the brain, so-called engram cells. To define a stable engram each region of the brain involved in memory storage recruits between 5 and 20 percent of excitatory neurons. In par ...

Edge-computing requires high-performance energy-efficient embedded systems. Fixed-function or custom accelerators, such as FFT or FIR filter engines, are very efficient at implementing a particular functionality for a given set of constraints. However, the ...

Recent advances in computational neuroscience have demonstrated the usefulness and importance of stochastic, spatial reaction-diffusion simulations. However, ever increasing model complexity renders traditional serial solvers, as well as naive parallel imp ...

Even if Dennard scaling came to an end fifteen years ago, Moore' s law kept fueling an exponential growth in compute performance through increased parallelization. However, the performance of memory and, in particular, Dynamic Random Access Memory (DRAM), ...

Memory chip or memory array for wide-voltage range in-memory computing using bitline technology

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Reinforcement Learning-Based Joint Reliability and Performance Optimization for Hybrid-Cache Computing Servers

AstriFlash: A Flash-Based System for Online Services

HPCache: Memory-Efficient OLAP Through Proportional Caching

Low-Power Artificial Neural Network Perceptron Based on Monolayer MoS2

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

Tuning paradigm of external stimuli driven electronic, optical and magnetic properties in hybrid perovskites and metalorganic complexes br

HyperLogLog: Exponentially Bad in Adversarial Settings

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge

An Accuracy-Driven Compression Methodology to Derive Efficient Codebook-Based CNNs

Epigenetic plasticity as a signature for memory allocation

VWR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

STEPS 4.0: Fast and memory-efficient molecular simulations of neurons at the nanoscale

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities