Publication

A Single-Photon Avalanche Diode Imager for Fluorescence Lifetime Applications

Publications associées (15)

High-Speed ADC Design and Optimization for Wireline Links

The ever-growing global internet traffic has increased demand for higher speed data transmission. As the bandwidth requirements of wireline links increase, extensive digital equalization techniques are required to compensate for the high-frequency channel ...

EPFL2021

Applications of a reconfigurable SPAD line imager

Claudio Bruschini, Edoardo Charbon, Samuel Burri

Single-photon avalanche diodes (SPADs) fabricated in standard CMOS processes enable cost-effective volume production of sensors capable of time-stamping individual photons with high accuracy. This capability makes the sensors ideally suited for application ...

2018

A time-gated large-array SPAD camera for picosecond resolution real-time FLIM

Claudio Bruschini, Edoardo Charbon, Arin Can Ülkü

Single-photon avalanche diode (SPAD) arrays have recently emerged as promising detectors for many wide-field fluorescence lifetime imaging microscopy (FLIM) applications, thanks to their picosecond range temporal resolution, single-photon sensitivity and f ...

2018

A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications

Edoardo Charbon, Harald Arjan Robert Homulle

We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmw ...

2016

Challenges and Solutions to Next-Generation Single-Photon Imagers

Samuel Burri

Detecting and counting single photons is useful in an increasingly large number of applications. Most applications require large formats, approaching and even far exceeding 1 megapixel. In this thesis, we look at the challenges of massively parallel photon ...

EPFL2016

Exploring information retrieval using image sparse representations : from circuit designs and acquisition processes to specific reconstruction algorithms

William Guicquéro

New advances in the field of image sensors (especially in CMOS technology) tend to question the conventional methods used to acquire the image. Compressive Sensing (CS) plays a major role in this, especially to unclog the Analog to Digital Converters which ...

EPFL2015

A Subthreshold Current-Sensing Sigma-Delta Modulator for Low-Voltage and Low-Power Sensor Interfaces

Alexandre Schmid, Yusuf Leblebici, Seyed Armin Tajalli, Nikola Katic

A continuous-time (CT) ΣΔ modulator for sensing and direct analog-to-digital conversion of nA-range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source-coupled logic cells to ...

Wiley2015

Design of Digital SoC for Operation at High Temperatures

Radisav Cojbasic

There is a growing demand for Systems-on-Chip, integrating microprocessors, on-chip memories, data converters and a variety of sensors, which are capable of reliable operation at high temperatures. For instance, modern aircraft industry demands microcontro ...

EPFL2014

Ultra high-speed electronics for power system dynamic emulation

Laurent Fabre

Modern society is dependent on reliable electricity for security, health, communication, transportation, finance, computers and nearly all aspects of the contemporary life. Providing reliable electricity is a very complex challenge. It involves real-time m ...

EPFL2013

Design and Exploration of Low-Power Analog to Information Conversion Based on Compressed Sensing

Pierre Vandergheynst, David Atienza Alonso, Nadia Khaled, Hossein Mamaghanian

The long-standing analog-to-digital conversion paradigm based on Shannon/Nyquist sampling has been challenged lately, mostly in situations such as radar and communication signal processing where signal bandwidth is so large that sampling architectures cons ...

2012

On-Chip Digital Background Calibration of Pipelined Analog-to-Digital Converters using Digital Assistance to support Nonlinear Residue Amplification

Thomas Liechti

This thesis describes a novel digital background calibration scheme for pipelined ADCs with nonlinear interstage gain. Errors caused by the nonlinear gains are corrected in real-time by adaptively post-processing the digital stage outputs. The goal of this ...

EPFL2012

Power-Efficient Pipelined Analog-to-Digital Converter Architectures for Advanced CMOS Technologies

Among different analog-to-digital converter (ADC) architectures pipelined ADCs are the most suited for medium sampling frequencies (50-300MSPS) and medium resolutions, i.e. 8 to 14 bits. Having the lowest figure-of-merit (FOM) in its bandwidth and resoluti ...

EPFL2012

3D Integration Technology for Lab-on-a-Chip Applications

Yüksel Temiz

This study adds a new dimension to lab-on-a-chip systems by employing three-dimensional (3D) integration technology for improved performance, higher functionality, and on-chip computational power. Despite the extensive amount of current research on 3D memo ...

EPFL2012

Parallel architecture for high-speed analog-to-digital conversion

Guillaume Ding

Nowadays digital signal processing systems used for radar applications, communication systems or RF measurement equipments, require very high sample-rates. Sometimes these sample-rates are beyond the possibilities offered by conventional ADCs. To overcome ...

EPFL2009

A standard CMOS multi-channel single-chip receiver for multi-gigabit optical data communications

Paul Victor Georges Muller

As dictated by ongoing technology scaling and the advent of multi-core systems, each new generation of microprocessors and digital signal processors provides higher computing power and data throughput. However, the available bandwidth of the input/output ( ...

EPFL2006