Publication

Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library

Publications associées (30)

At the end of scaling: 2D materials for computing and sensing applications

In the past half-century, the digital revolution completely changed the world we live in and the ways we experience it. Over this period, the underlying force supporting the continuous technological development has been the geometrical scaling of transisto ...

EPFL2020

A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS

Yusuf Leblebici, Ayça Akkaya, Firat Çelik

This paper presents a 9-bit 222 MS/s low-power asynchronous single-bit/cycle successive approximation register (SAR) ADC. The SAR ADC combines techniques such as asynchronous clocking, binary-weighted custom-designed capacitive DAC with small unit capacito ...

IEEE2020

Data Structures and Algorithms for Logic Synthesis in Advanced Technologies

Eleonora Testa

Logic synthesis is a key component of digital design and modern EDA tools; it is thus an essential instrument for the design of leading-edge chips and to push the limits of their performance. In the last decades, the electronic circuits community has evolv ...

EPFL2020

Logic-in-memory based on an atomically thin semiconductor

Andras Kis, Aleksandra Radenovic, Yanfei Zhao, Ahmet Avsar, Zhenyu Wang, Guilherme Migliato Marega, Mukesh Kumar Tripathi

The growing importance of applications based on machine learning is driving the need to develop dedicated, energy-efficient electronic hardware. Compared with von Neumann architectures, which have separate processing and storage units, brain-inspired in-me ...

2020

Reconfigurable Logic Gates Based on Programable Multistable Mechanisms

Simon Nessim Henein, Ilan Vardi, Mohamed Gamal Abdelrahman Ahmed Zanaty, Hubert Pierre-Marie Benoît Schneegans

Binary logic gates are building blocks of computing machines, in particular, electronic computers. One variant is the programable logic gate, also known as the reconfigurable logic gate, in which the logical function implemented can be modified. In this pa ...

2020

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Edoardo Charbon, Fabio Sebastiano

Cryogenic device models are essential for the reliable design of the cryo-CMOS electronic interface necessary to build future large-scale quantum computers. This paper reports the characterization of the drain-current mismatch of NMOS and PMOS devices fabr ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Ionizing-Radiation Response and Low-Frequency Noise of 28-nm MOSFETs at Ultrahigh Doses

Christian Enz

Total ionizing dose (TID) mechanisms are investigated in 28-nm MOSFETs via dc static and low-frequency noise measurements. nMOSFETs and pMOSFETs are irradiated up to 1 Grad(SiO2) and annealed at high temperatures. TID sensitivity depends on the channel len ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

A machine learning approach for power gating the FPGA routing network

Mirjana Stojilovic, Hossein Asadi

Power gating is a common approach for reducing circuit static power consumption. In FPGAs, resources that dominate static power consumption lie in the routing network. Researchers have proposed several heuristics for clustering multiplexers in the routing ...

IEEE COMPUTER SOC2019

Polarity-Controllable Devices and Circuits for Doping-Free 2D Electronics

Giovanni Vincenzo Resta

The growth of information technology has been sustained by the miniaturization of Complementary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors (FETs), with the number of devices per unit area constantly increasing, as exemplified by Mooreâ s la ...

EPFL2019

Exploration of Negative Capacitance Devices and Technologies

Ali Saeidi

Conventional device scaling has been the main guiding principle of the MOS device engineering over these past years. However, this aggressive scaling would be eventually limited due to the inability to remove the heat generated by MOSFET devices. The power ...

EPFL2019